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Clean-up merge problems
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Signed-off-by: Florian Zaruba <[email protected]>
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@zarubaf
zarubaf committed Sep 14, 2023
1 parent 6a8c82b commit 9927f6b
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Showing 19 changed files with 568 additions and 354 deletions.
2 changes: 1 addition & 1 deletion core/cache_subsystem/cva6_icache.sv
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Expand Up @@ -130,7 +130,7 @@ module cva6_icache import ariane_pkg::*; import wt_cache_pkg::*; #(
assign cl_index = vaddr_d[ICACHE_INDEX_WIDTH-1:ICACHE_OFFSET_WIDTH];


if (CVA6Cfg.NOCType == ariane_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_offset
if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_offset
// if we generate a noncacheable access, the word will be at offset 0 or 4 in the cl coming from memory
assign cl_offset_d = ( dreq_o.ready & dreq_i.req) ? {dreq_i.vaddr>>2, 2'b0} :
( paddr_is_nc & mem_data_req_o ) ? cl_offset_q[2]<<2 : // needed since we transfer 32bit over a 64bit AXI bus in this case
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2 changes: 1 addition & 1 deletion core/cache_subsystem/wt_dcache_mem.sv
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Expand Up @@ -255,7 +255,7 @@ module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #(
assign wbuffer_ruser = wbuffer_data_i[wbuffer_hit_idx].user;
assign wbuffer_be = (|wbuffer_hit_oh) ? wbuffer_data_i[wbuffer_hit_idx].valid : '0;

if (CVA6Cfg.NOCType == ariane_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_offset
if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_offset
// In case of an uncached read, return the desired XLEN-bit segment of the most recent AXI read
assign wr_cl_off = (wr_cl_nc_i) ? (CVA6Cfg.AxiDataWidth == riscv::XLEN) ? '0 :
wr_cl_off_i[AXI_OFFSET_WIDTH-1:riscv::XLEN_ALIGN_BYTES] :
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2 changes: 1 addition & 1 deletion core/cache_subsystem/wt_dcache_missunit.sv
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Expand Up @@ -254,7 +254,7 @@ module wt_dcache_missunit import ariane_pkg::*; import wt_cache_pkg::*; #(
end

// note: openpiton returns a full cacheline!
if (CVA6Cfg.NOCType == ariane_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_rtrn_mux
if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_rtrn_mux
if (CVA6Cfg.AxiDataWidth > 64) begin
assign amo_rtrn_mux = mem_rtrn_i.data[amo_req_i.operand_a[$clog2(CVA6Cfg.AxiDataWidth/8)-1:3]*64 +: 64];
end else begin
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4 changes: 2 additions & 2 deletions core/cache_subsystem/wt_l15_adapter.sv
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Expand Up @@ -132,8 +132,8 @@ l15_rtrn_t rtrn_fifo_data;


// openpiton is big endian
if (CVA6Cfg.NOCType == ariane_pkg::NOC_TYPE_L15_BIG_ENDIAN) assign l15_req_o.l15_data = swendian64(dcache_data.data);
else if (CVA6Cfg.NOCType == ariane_pkg::NOC_TYPE_L15_LITTLE_ENDIAN) assign l15_req_o.l15_data = dcache_data.data;
if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_L15_BIG_ENDIAN) assign l15_req_o.l15_data = swendian64(dcache_data.data);
else if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_L15_LITTLE_ENDIAN) assign l15_req_o.l15_data = dcache_data.data;
else $fatal(1,"[wt_l15_adapter] Unsupported NOC type");

// arbiter
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2 changes: 1 addition & 1 deletion core/csr_regfile.sv
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Expand Up @@ -907,7 +907,7 @@ module csr_regfile import ariane_pkg::*; #(
mstatus_d.sd = (mstatus_q.xs == riscv::Dirty) | (mstatus_q.fs == riscv::Dirty);

// reserve PMPCFG bits 5 and 6 (hardwire to 0)
for (int i = 0; i < NrPMPEntries; i++) pmpcfg_d[i].reserved = 2'b0;
for (int i = 0; i < CVA6Cfg.NrPMPEntries; i++) pmpcfg_d[i].reserved = 2'b0;

// write the floating point status register
if (csr_write_fflags_i) begin
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19 changes: 17 additions & 2 deletions core/cva6.sv
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Expand Up @@ -191,7 +191,22 @@ module cva6 import ariane_pkg::*; #(
unsigned'(NrWbPorts),
bit'(EnableAccelerator),
CVA6Cfg.HaltAddress,
CVA6Cfg.ExceptionAddress
CVA6Cfg.ExceptionAddress,
CVA6Cfg.RASDepth,
CVA6Cfg.BTBEntries,
CVA6Cfg.BHTEntries,
CVA6Cfg.DmBaseAddress,
CVA6Cfg.NrPMPEntries,
CVA6Cfg.NOCType,
CVA6Cfg.NrNonIdempotentRules,
CVA6Cfg.NonIdempotentAddrBase,
CVA6Cfg.NonIdempotentLength,
CVA6Cfg.NrExecuteRegionRules,
CVA6Cfg.ExecuteRegionAddrBase,
CVA6Cfg.ExecuteRegionLength,
CVA6Cfg.NrCachedRegionRules,
CVA6Cfg.CachedRegionAddrBase,
CVA6Cfg.CachedRegionLength
};


Expand Down Expand Up @@ -429,7 +444,7 @@ module cva6 import ariane_pkg::*; #(
// Frontend
// --------------
frontend #(
.CVA6Cfg ( CVA6ExtendCfg ),
.CVA6Cfg ( CVA6ExtendCfg )
) i_frontend (
.flush_i ( flush_ctrl_if ), // not entirely correct
.flush_bp_i ( 1'b0 ),
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10 changes: 5 additions & 5 deletions core/include/config_pkg.sv
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Expand Up @@ -34,12 +34,12 @@ package config_pkg;
/// ports than issue ports, for the scoreboard to empty out in case one
/// instruction stalls a little longer.
int unsigned NrCommitPorts;
int unsigned IsRVFI;
/// AXI parameters.
int unsigned AxiAddrWidth;
int unsigned AxiDataWidth;
int unsigned AxiIdWidth;
int unsigned AxiUserWidth;
int unsigned NrLoadBufEntries;
bit FpuEn;
bit XF16;
bit XF16ALT;
Expand Down Expand Up @@ -131,11 +131,11 @@ package config_pkg;
EnableAccelerator: bit'(0),
HaltAddress: 64'h800,
ExceptionAddress: 64'h808,
RASDepth: unsigned'(cva6_config_pkg::CVA6ConfigRASDepth),
BTBEntries: unsigned'(cva6_config_pkg::CVA6ConfigBTBEntries),
BHTEntries: unsigned'(cva6_config_pkg::CVA6ConfigBHTEntries),
RASDepth: 2,
BTBEntries: 32,
BHTEntries: 128,
DmBaseAddress: 64'h0,
NrPMPEntries: unsigned'(cva6_config_pkg::CVA6ConfigNrPMPEntries),
NrPMPEntries: 8,
NOCType: NOC_TYPE_AXI4_ATOP,
// idempotent region
NrNonIdempotentRules: unsigned'(2),
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80 changes: 49 additions & 31 deletions core/include/cv32a60x_config_pkg.sv
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Expand Up @@ -75,37 +75,55 @@ package cva6_config_pkg;

localparam CVA6ConfigRvfiTrace = 1;

localparam config_pkg::cva6_cfg_t cva6_cfg = {
unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts
unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth
unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth
unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth
unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth
unsigned'(CVA6ConfigNrLoadBufEntries), // NrLoadBufEntries
bit'(CVA6ConfigFpuEn), // FpuEn
bit'(CVA6ConfigF16En), // XF16
bit'(CVA6ConfigF16AltEn), // XF16ALT
bit'(CVA6ConfigF8En), // XF8
bit'(CVA6ConfigAExtEn), // RVA
bit'(CVA6ConfigVExtEn), // RVV
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
localparam config_pkg::cva6_cfg_t cva6_cfg = '{
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
FpuEn: bit'(CVA6ConfigFpuEn),
XF16: bit'(CVA6ConfigF16En),
XF16ALT: bit'(CVA6ConfigF16AltEn),
XF8: bit'(CVA6ConfigF8En),
RVA: bit'(CVA6ConfigAExtEn),
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
XFVec: bit'(CVA6ConfigFVecEn),
CvxifEn: bit'(CVA6ConfigCvxifEn),
// Extended
bit'(0), // RVF
bit'(0), // RVD
bit'(0), // FpPresent
bit'(0), // NSX
unsigned'(0), // FLen
bit'(0), // RVFVec
bit'(0), // XF16Vec
bit'(0), // XF16ALTVec
bit'(0), // XF8Vec
unsigned'(0), // NrRgprPorts
unsigned'(0), // NrWbPorts
bit'(0), // EnableAccelerator
64'h800, // HaltAddress
64'h808 // ExceptionAddress
} ;
RVF: bit'(0),
RVD: bit'(0),
FpPresent: bit'(0),
NSX: bit'(0),
FLen: unsigned'(0),
RVFVec: bit'(0),
XF16Vec: bit'(0),
XF16ALTVec: bit'(0),
XF8Vec: bit'(0),
NrRgprPorts: unsigned'(0),
NrWbPorts: unsigned'(0),
EnableAccelerator: bit'(0),
HaltAddress: 64'h800,
ExceptionAddress: 64'h808,
RASDepth: unsigned'(CVA6ConfigRASDepth),
BTBEntries: unsigned'(CVA6ConfigBTBEntries),
BHTEntries: unsigned'(CVA6ConfigBHTEntries),
DmBaseAddress: 64'h0,
NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries),
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
// idempotent region
NrNonIdempotentRules: unsigned'(2),
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrExecuteRegionRules: unsigned'(3),
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
// cached region
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({64'h8000_0000}),
CachedRegionLength: 1024'({64'h40000000})
};

endpackage
80 changes: 49 additions & 31 deletions core/include/cv32a6_embedded_config_pkg.sv
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Expand Up @@ -74,37 +74,55 @@ package cva6_config_pkg;

localparam CVA6ConfigRvfiTrace = 1;

localparam config_pkg::cva6_cfg_t cva6_cfg = {
unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts
unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth
unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth
unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth
unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth
unsigned'(CVA6ConfigNrLoadBufEntries), // NrLoadBufEntries
bit'(CVA6ConfigFpuEn), // FpuEn
bit'(CVA6ConfigF16En), // XF16
bit'(CVA6ConfigF16AltEn), // XF16ALT
bit'(CVA6ConfigF8En), // XF8
bit'(CVA6ConfigAExtEn), // RVA
bit'(CVA6ConfigVExtEn), // RVV
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
localparam config_pkg::cva6_cfg_t cva6_cfg = '{
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
FpuEn: bit'(CVA6ConfigFpuEn),
XF16: bit'(CVA6ConfigF16En),
XF16ALT: bit'(CVA6ConfigF16AltEn),
XF8: bit'(CVA6ConfigF8En),
RVA: bit'(CVA6ConfigAExtEn),
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
XFVec: bit'(CVA6ConfigFVecEn),
CvxifEn: bit'(CVA6ConfigCvxifEn),
// Extended
bit'(0), // RVF
bit'(0), // RVD
bit'(0), // FpPresent
bit'(0), // NSX
unsigned'(0), // FLen
bit'(0), // RVFVec
bit'(0), // XF16Vec
bit'(0), // XF16ALTVec
bit'(0), // XF8Vec
unsigned'(0), // NrRgprPorts
unsigned'(0), // NrWbPorts
bit'(0), // EnableAccelerator
64'h800, // HaltAddress
64'h808 // ExceptionAddress
} ;
RVF: bit'(0),
RVD: bit'(0),
FpPresent: bit'(0),
NSX: bit'(0),
FLen: unsigned'(0),
RVFVec: bit'(0),
XF16Vec: bit'(0),
XF16ALTVec: bit'(0),
XF8Vec: bit'(0),
NrRgprPorts: unsigned'(0),
NrWbPorts: unsigned'(0),
EnableAccelerator: bit'(0),
HaltAddress: 64'h800,
ExceptionAddress: 64'h808,
RASDepth: unsigned'(CVA6ConfigRASDepth),
BTBEntries: unsigned'(CVA6ConfigBTBEntries),
BHTEntries: unsigned'(CVA6ConfigBHTEntries),
DmBaseAddress: 64'h0,
NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries),
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
// idempotent region
NrNonIdempotentRules: unsigned'(2),
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrExecuteRegionRules: unsigned'(3),
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
// cached region
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({64'h8000_0000}),
CachedRegionLength: 1024'({64'h40000000})
};

endpackage
80 changes: 49 additions & 31 deletions core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
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Expand Up @@ -75,37 +75,55 @@ package cva6_config_pkg;

localparam CVA6ConfigRvfiTrace = 1;

localparam config_pkg::cva6_cfg_t cva6_cfg = {
unsigned'(CVA6ConfigNrCommitPorts), // NrCommitPorts
unsigned'(CVA6ConfigAxiAddrWidth), // AxiAddrWidth
unsigned'(CVA6ConfigAxiDataWidth), // AxiDataWidth
unsigned'(CVA6ConfigAxiIdWidth), // AxiIdWidth
unsigned'(CVA6ConfigDataUserWidth), // AxiUserWidth
unsigned'(CVA6ConfigNrLoadBufEntries), // NrLoadBufEntries
bit'(CVA6ConfigFpuEn), // FpuEn
bit'(CVA6ConfigF16En), // XF16
bit'(CVA6ConfigF16AltEn), // XF16ALT
bit'(CVA6ConfigF8En), // XF8
bit'(CVA6ConfigAExtEn), // RVA
bit'(CVA6ConfigVExtEn), // RVV
bit'(CVA6ConfigCExtEn), // RVC
bit'(CVA6ConfigFVecEn), // XFVec
bit'(CVA6ConfigCvxifEn), // CvxifEn
localparam config_pkg::cva6_cfg_t cva6_cfg = '{
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
FpuEn: bit'(CVA6ConfigFpuEn),
XF16: bit'(CVA6ConfigF16En),
XF16ALT: bit'(CVA6ConfigF16AltEn),
XF8: bit'(CVA6ConfigF8En),
RVA: bit'(CVA6ConfigAExtEn),
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
XFVec: bit'(CVA6ConfigFVecEn),
CvxifEn: bit'(CVA6ConfigCvxifEn),
// Extended
bit'(0), // RVF
bit'(0), // RVD
bit'(0), // FpPresent
bit'(0), // NSX
unsigned'(0), // FLen
bit'(0), // RVFVec
bit'(0), // XF16Vec
bit'(0), // XF16ALTVec
bit'(0), // XF8Vec
unsigned'(0), // NrRgprPorts
unsigned'(0), // NrWbPorts
bit'(0), // EnableAccelerator
64'h800, // HaltAddress
64'h808 // ExceptionAddress
} ;
RVF: bit'(0),
RVD: bit'(0),
FpPresent: bit'(0),
NSX: bit'(0),
FLen: unsigned'(0),
RVFVec: bit'(0),
XF16Vec: bit'(0),
XF16ALTVec: bit'(0),
XF8Vec: bit'(0),
NrRgprPorts: unsigned'(0),
NrWbPorts: unsigned'(0),
EnableAccelerator: bit'(0),
HaltAddress: 64'h800,
ExceptionAddress: 64'h808,
RASDepth: unsigned'(CVA6ConfigRASDepth),
BTBEntries: unsigned'(CVA6ConfigBTBEntries),
BHTEntries: unsigned'(CVA6ConfigBHTEntries),
DmBaseAddress: 64'h0,
NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries),
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
// idempotent region
NrNonIdempotentRules: unsigned'(2),
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrExecuteRegionRules: unsigned'(3),
// DRAM, Boot ROM, Debug Module
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
// cached region
NrCachedRegionRules: unsigned'(1),
CachedRegionAddrBase: 1024'({64'h8000_0000}),
CachedRegionLength: 1024'({64'h40000000})
};

endpackage
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