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Add Direct D$ Access to acc_dispatcher (#1361)
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@JeanRochCoulon
JeanRochCoulon authored Sep 5, 2023
2 parents d9ad16b + d45fda6 commit 885be3c
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Showing 8 changed files with 150 additions and 109 deletions.
3 changes: 3 additions & 0 deletions core/acc_dispatcher.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,8 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; #(
input logic flush_ex_i,
output logic flush_pipeline_o,
// Interface with cache subsystem
output dcache_req_i_t [1:0] acc_dcache_req_ports_o,
input dcache_req_o_t [1:0] acc_dcache_req_ports_i,
input logic inval_ready_i,
output logic inval_valid_o,
output logic [63:0] inval_addr_o,
Expand Down Expand Up @@ -412,5 +414,6 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; #(

assign acc_stall_st_pending_o = 1'b0;
assign flush_pipeline_o = 1'b0;
assign acc_dcache_req_ports_o = '0;

endmodule : acc_dispatcher
6 changes: 3 additions & 3 deletions core/cache_subsystem/miss_handler.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@

module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter int unsigned NR_PORTS = 3,
parameter int unsigned NR_PORTS = 4,
parameter type axi_req_t = logic,
parameter type axi_rsp_t = logic
)(
Expand Down Expand Up @@ -524,7 +524,7 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #(
bypass_ports_req[id].req = miss_req_valid[id] & miss_req_bypass[id];
bypass_ports_req[id].reqtype = ariane_pkg::SINGLE_REQ;
bypass_ports_req[id].amo = AMO_NONE;
bypass_ports_req[id].id = {2'b10, id};
bypass_ports_req[id].id = 4'b1000 | 4'(id);
bypass_ports_req[id].addr = miss_req_addr[id];
bypass_ports_req[id].wdata = miss_req_wdata[id];
bypass_ports_req[id].we = miss_req_we[id];
Expand Down Expand Up @@ -619,7 +619,7 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #(
.wdata_i ( req_fsm_miss_wdata ),
.be_i ( req_fsm_miss_be ),
.size_i ( req_fsm_miss_size ),
.id_i ( {{CVA6Cfg.AxiIdWidth-4{1'b0}}, 4'b1100} ),
.id_i ( {{CVA6Cfg.AxiIdWidth-4{1'b0}}, 4'b0111} ),
.valid_o ( valid_miss_fsm ),
.rdata_o ( data_miss_fsm ),
.id_o ( ),
Expand Down
49 changes: 26 additions & 23 deletions core/cache_subsystem/std_cache_subsystem.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@
module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions
parameter int unsigned NumPorts = 4,
parameter type axi_ar_chan_t = logic,
parameter type axi_aw_chan_t = logic,
parameter type axi_w_chan_t = logic,
Expand Down Expand Up @@ -48,8 +49,8 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
output logic dcache_miss_o, // we missed on a ld/st
output logic wbuffer_empty_o, // statically set to 1, as there is no wbuffer in this cache system
// Request ports
input dcache_req_i_t [2:0] dcache_req_ports_i, // to/from LSU
output dcache_req_o_t [2:0] dcache_req_ports_o, // to/from LSU
input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // to/from LSU
output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to/from LSU
// memory side
output axi_req_t axi_req_o,
input axi_rsp_t axi_resp_i
Expand Down Expand Up @@ -87,10 +88,12 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
// decreasing priority
// Port 0: PTW
// Port 1: Load Unit
// Port 2: Store Unit
// Port 2: Accelerator
// Port 3: Store Unit
std_nbdcache #(
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg ),
.NumPorts ( NumPorts ),
.axi_req_t ( axi_req_t ),
.axi_rsp_t ( axi_rsp_t )
) i_nbdcache (
Expand Down Expand Up @@ -151,10 +154,10 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
// to forward the correct write data.
always_comb begin
w_select = 0;
unique case (axi_req_o.aw.id)
4'b1100: w_select = 2; // dcache
4'b1000, 4'b1001, 4'b1010, 4'b1011: w_select = 1; // bypass
default: w_select = 0; // icache
unique casez (axi_req_o.aw.id)
4'b0111: w_select = 2; // dcache
4'b1???: w_select = 1; // bypass
default: w_select = 0; // icache
endcase
end

Expand Down Expand Up @@ -199,9 +202,9 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
);

// Route responses based on ID
// 0000 -> I$
// 10[00|10|01|11] -> Bypass
// 1100 -> D$
// 0000 -> I$
// 0111 -> D$
// 1??? -> Bypass
// R Channel
assign axi_resp_icache.r = axi_resp_i.r;
assign axi_resp_bypass.r = axi_resp_i.r;
Expand All @@ -211,11 +214,11 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(

always_comb begin
r_select = 0;
unique case (axi_resp_i.r.id)
4'b1100: r_select = 0; // dcache
4'b1000, 4'b1001, 4'b1010, 4'b1011: r_select = 1; // bypass
4'b0000: r_select = 2; // icache
default: r_select = 0;
unique casez (axi_resp_i.r.id)
4'b0111: r_select = 0; // dcache
4'b1???: r_select = 1; // bypass
4'b0000: r_select = 2; // icache
default: r_select = 0;
endcase
end

Expand All @@ -238,11 +241,11 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(

always_comb begin
b_select = 0;
unique case (axi_resp_i.b.id)
4'b1100: b_select = 0; // dcache
4'b1000, 4'b1001, 4'b1010, 4'b1011: b_select = 1; // bypass
4'b0000: b_select = 2; // icache
default: b_select = 0;
unique casez (axi_resp_i.b.id)
4'b0111: b_select = 0; // dcache
4'b1???: b_select = 1; // bypass
4'b0000: b_select = 2; // icache
default: b_select = 0;
endcase
end

Expand All @@ -269,11 +272,11 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
icache_dreq_o.vaddr, icache_dreq_o.data);

a_invalid_write_data: assert property (
@(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_i[2].data_req |-> |dcache_req_ports_i[2].data_be |-> (|dcache_req_ports_i[2].data_wdata) !== 1'hX)
@(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_i[NumPorts-1].data_req |-> |dcache_req_ports_i[NumPorts-1].data_be |-> (|dcache_req_ports_i[NumPorts-1].data_wdata) !== 1'hX)
else $warning(1,"[l1 dcache] writing invalid data: paddr=%016X, be=%02X, data=%016X",
{dcache_req_ports_i[2].address_tag, dcache_req_ports_i[2].address_index}, dcache_req_ports_i[2].data_be, dcache_req_ports_i[2].data_wdata);
{dcache_req_ports_i[NumPorts-1].address_tag, dcache_req_ports_i[NumPorts-1].address_index}, dcache_req_ports_i[NumPorts-1].data_be, dcache_req_ports_i[NumPorts-1].data_wdata);
generate
for(genvar j=0; j<2; j++) begin
for(genvar j=0; j<NumPorts-1; j++) begin
a_invalid_read_data: assert property (
@(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_o[j].data_rvalid |-> (|dcache_req_ports_o[j].data_rdata) !== 1'hX)
else $warning(1,"[l1 dcache] reading invalid data on port %01d: data=%016X",
Expand Down
56 changes: 29 additions & 27 deletions core/cache_subsystem/std_nbdcache.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@
module std_nbdcache import std_cache_pkg::*; import ariane_pkg::*; #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions
parameter int unsigned NumPorts = 4,
parameter type axi_req_t = logic,
parameter type axi_rsp_t = logic
)(
Expand All @@ -30,8 +31,8 @@ module std_nbdcache import std_cache_pkg::*; import ariane_pkg::*; #(
input amo_req_t amo_req_i,
output amo_resp_t amo_resp_o,
// Request ports
input dcache_req_i_t [2:0] req_ports_i, // request ports
output dcache_req_o_t [2:0] req_ports_o, // request ports
input dcache_req_i_t [NumPorts-1:0] req_ports_i, // request ports
output dcache_req_o_t [NumPorts-1:0] req_ports_o, // request ports
// Cache AXI refill port
output axi_req_t axi_data_o,
input axi_rsp_t axi_data_i,
Expand All @@ -47,34 +48,35 @@ import std_cache_pkg::*;
// 1. Miss handler
// 2. PTW
// 3. Load Unit
// 4. Store unit
logic [3:0][DCACHE_SET_ASSOC-1:0] req;
logic [3:0][DCACHE_INDEX_WIDTH-1:0]addr;
logic [3:0] gnt;
cache_line_t [DCACHE_SET_ASSOC-1:0] rdata;
logic [3:0][DCACHE_TAG_WIDTH-1:0] tag;
// 4. Accelerator
// 5. Store unit
logic [NumPorts:0][DCACHE_SET_ASSOC-1:0] req;
logic [NumPorts:0][DCACHE_INDEX_WIDTH-1:0]addr;
logic [NumPorts:0] gnt;
cache_line_t [DCACHE_SET_ASSOC-1:0] rdata;
logic [NumPorts:0][DCACHE_TAG_WIDTH-1:0] tag;

cache_line_t [3:0] wdata;
logic [3:0] we;
cl_be_t [3:0] be;
logic [DCACHE_SET_ASSOC-1:0] hit_way;
cache_line_t [NumPorts:0] wdata;
logic [NumPorts:0] we;
cl_be_t [NumPorts:0] be;
logic [DCACHE_SET_ASSOC-1:0] hit_way;
// -------------------------------
// Controller <-> Miss unit
// -------------------------------
logic [2:0] busy;
logic [2:0][55:0] mshr_addr;
logic [2:0] mshr_addr_matches;
logic [2:0] mshr_index_matches;
logic [63:0] critical_word;
logic critical_word_valid;
logic [NumPorts-1:0] busy;
logic [NumPorts-1:0][55:0] mshr_addr;
logic [NumPorts-1:0] mshr_addr_matches;
logic [NumPorts-1:0] mshr_index_matches;
logic [63:0] critical_word;
logic critical_word_valid;

logic [2:0][$bits(miss_req_t)-1:0] miss_req;
logic [2:0] miss_gnt;
logic [2:0] active_serving;
logic [NumPorts-1:0][$bits(miss_req_t)-1:0] miss_req;
logic [NumPorts-1:0] miss_gnt;
logic [NumPorts-1:0] active_serving;

logic [2:0] bypass_gnt;
logic [2:0] bypass_valid;
logic [2:0][63:0] bypass_data;
logic [NumPorts-1:0] bypass_gnt;
logic [NumPorts-1:0] bypass_valid;
logic [NumPorts-1:0][63:0] bypass_data;
// -------------------------------
// Arbiter <-> Datram,
// -------------------------------
Expand All @@ -89,7 +91,7 @@ import std_cache_pkg::*;
// Cache Controller
// ------------------
generate
for (genvar i = 0; i < 3; i++) begin : master_ports
for (genvar i = 0; i < NumPorts; i++) begin : master_ports
cache_ctrl #(
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg )
Expand Down Expand Up @@ -132,7 +134,7 @@ import std_cache_pkg::*;
// ------------------
miss_handler #(
.CVA6Cfg ( CVA6Cfg ),
.NR_PORTS ( 3 ),
.NR_PORTS ( NumPorts ),
.axi_req_t ( axi_req_t ),
.axi_rsp_t ( axi_rsp_t )
) i_miss_handler (
Expand Down Expand Up @@ -243,7 +245,7 @@ import std_cache_pkg::*;
// ------------------------------------------------
tag_cmp #(
.CVA6Cfg ( CVA6Cfg ),
.NR_PORTS ( 4 ),
.NR_PORTS ( NumPorts+1 ),
.ADDR_WIDTH ( DCACHE_INDEX_WIDTH ),
.DCACHE_SET_ASSOC ( DCACHE_SET_ASSOC )
) i_tag_cmp (
Expand Down
12 changes: 6 additions & 6 deletions core/cache_subsystem/wt_cache_subsystem.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@
module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig, // contains cacheable regions
parameter int unsigned NumPorts = 3,
parameter int unsigned NumPorts = 4,
parameter type noc_req_t = logic,
parameter type noc_resp_t = logic
) (
Expand Down Expand Up @@ -50,8 +50,8 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
input amo_req_t dcache_amo_req_i,
output amo_resp_t dcache_amo_resp_o,
// Request ports
input dcache_req_i_t [2:0] dcache_req_ports_i, // to/from LSU
output dcache_req_o_t [2:0] dcache_req_ports_o, // to/from LSU
input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // to/from LSU
output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to/from LSU
// writebuffer status
output logic wbuffer_empty_o,
output logic wbuffer_not_ni_o,
Expand Down Expand Up @@ -193,13 +193,13 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(

for (genvar j=0; j<riscv::XLEN/8; j++) begin : gen_invalid_write_assertion
a_invalid_write_data: assert property (
@(posedge clk_i) disable iff (!rst_ni) dcache_req_ports_i[2].data_req |-> dcache_req_ports_i[2].data_be[j] |-> (|dcache_req_ports_i[2].data_wdata[j*8+:8] !== 1'hX))
@(posedge clk_i) disable iff (!rst_ni) dcache_req_ports_i[NumPorts-1].data_req |-> dcache_req_ports_i[NumPorts-1].data_be[j] |-> (|dcache_req_ports_i[NumPorts-1].data_wdata[j*8+:8] !== 1'hX))
else $warning(1,"[l1 dcache] writing invalid data: paddr=%016X, be=%02X, data=%016X, databe=%016X",
{dcache_req_ports_i[2].address_tag, dcache_req_ports_i[2].address_index}, dcache_req_ports_i[2].data_be, dcache_req_ports_i[2].data_wdata, dcache_req_ports_i[2].data_be & dcache_req_ports_i[2].data_wdata);
{dcache_req_ports_i[NumPorts-1].address_tag, dcache_req_ports_i[NumPorts-1].address_index}, dcache_req_ports_i[NumPorts-1].data_be, dcache_req_ports_i[NumPorts-1].data_wdata, dcache_req_ports_i[NumPorts-1].data_be & dcache_req_ports_i[NumPorts-1].data_wdata);
end


for (genvar j=0; j<2; j++) begin : gen_assertion
for (genvar j=0; j<NumPorts-1; j++) begin : gen_assertion
a_invalid_read_data: assert property (
@(posedge clk_i) disable iff (!rst_ni) dcache_req_ports_o[j].data_rvalid && ~dcache_req_ports_i[j].kill_req |-> (|dcache_req_ports_o[j].data_rdata) !== 1'hX)
else $warning(1,"[l1 dcache] reading invalid data on port %01d: data=%016X",
Expand Down
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