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Fully deprecate ariane_cfg_t
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Signed-off-by: Florian Zaruba <[email protected]>
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@zarubaf
zarubaf committed Jul 26, 2023
1 parent 1617a00 commit 8731c6b
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Showing 33 changed files with 150 additions and 229 deletions.
5 changes: 2 additions & 3 deletions core/cache_subsystem/cache_ctrl.sv
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Expand Up @@ -19,8 +19,7 @@


module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig // contains cacheable regions
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
Expand Down Expand Up @@ -248,7 +247,7 @@ module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #(
// -------------------------
// Check for cache-ability
// -------------------------
if (!is_inside_cacheable_regions(ArianeCfg, {{{64-riscv::PLEN}{1'b0}}, tag_o, {DCACHE_INDEX_WIDTH{1'b0}}})) begin
if (!is_inside_cacheable_regions(CVA6Cfg, {{{64-riscv::PLEN}{1'b0}}, tag_o, {DCACHE_INDEX_WIDTH{1'b0}}})) begin
mem_req_d.bypass = 1'b1;
state_d = WAIT_REFILL_GNT;
end
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9 changes: 4 additions & 5 deletions core/cache_subsystem/cva6_icache.sv
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Expand Up @@ -27,8 +27,7 @@

module cva6_icache import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter logic [MEM_TID_WIDTH-1:0] RdTxId = 0, // ID to be used for read transactions
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig // contains cacheable regions
parameter logic [MEM_TID_WIDTH-1:0] RdTxId = 0
) (
input logic clk_i,
input logic rst_ni,
Expand Down Expand Up @@ -113,7 +112,7 @@ module cva6_icache import ariane_pkg::*; import wt_cache_pkg::*; #(
assign cl_tag_d = (areq_i.fetch_valid) ? areq_i.fetch_paddr[ICACHE_TAG_WIDTH+ICACHE_INDEX_WIDTH-1:ICACHE_INDEX_WIDTH] : cl_tag_q;

// noncacheable if request goes to I/O space, or if cache is disabled
assign paddr_is_nc = (~cache_en_q) | (~ariane_pkg::is_inside_cacheable_regions(ArianeCfg, {{{64-riscv::PLEN}{1'b0}}, cl_tag_d, {ICACHE_INDEX_WIDTH{1'b0}}}));
assign paddr_is_nc = (~cache_en_q) | (~ariane_pkg::is_inside_cacheable_regions(CVA6Cfg, {{{64-riscv::PLEN}{1'b0}}, cl_tag_d, {ICACHE_INDEX_WIDTH{1'b0}}}));

// pass exception through
assign dreq_o.ex = areq_i.fetch_exception;
Expand All @@ -127,7 +126,7 @@ module cva6_icache import ariane_pkg::*; import wt_cache_pkg::*; #(
assign cl_index = vaddr_d[ICACHE_INDEX_WIDTH-1:ICACHE_OFFSET_WIDTH];


if (ArianeCfg.AxiCompliant) begin : gen_axi_offset
if (CVA6Cfg.BusType == ariane_pkg::BUS_TYPE_AXI4_ATOP) begin : gen_axi_offset
// if we generate a noncacheable access, the word will be at offset 0 or 4 in the cl coming from memory
assign cl_offset_d = ( dreq_o.ready & dreq_i.req) ? {dreq_i.vaddr>>2, 2'b0} :
( paddr_is_nc & mem_data_req_o ) ? cl_offset_q[2]<<2 : // needed since we transfer 32bit over a 64bit AXI bus in this case
Expand Down Expand Up @@ -161,7 +160,7 @@ end else begin : gen_piton_offset
// main control logic
///////////////////////////////////////////////////////
logic addr_ni;
assign addr_ni = is_inside_nonidempotent_regions(ArianeCfg, areq_i.fetch_paddr);
assign addr_ni = is_inside_nonidempotent_regions(CVA6Cfg, areq_i.fetch_paddr);
always_comb begin : p_fsm
// default assignment
state_d = state_q;
Expand Down
4 changes: 1 addition & 3 deletions core/cache_subsystem/cva6_icache_axi_wrapper.sv
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Expand Up @@ -15,7 +15,6 @@

module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions
parameter type axi_req_t = logic,
parameter type axi_rsp_t = logic
) (
Expand Down Expand Up @@ -99,8 +98,7 @@ module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; #(
cva6_icache #(
// use ID 0 for icache reads
.CVA6Cfg ( CVA6Cfg ),
.RdTxId ( 0 ),
.ArianeCfg ( ArianeCfg )
.RdTxId ( 0 )
) i_cva6_icache (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
Expand Down
3 changes: 0 additions & 3 deletions core/cache_subsystem/std_cache_subsystem.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,6 @@

module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions
parameter type axi_ar_chan_t = logic,
parameter type axi_aw_chan_t = logic,
parameter type axi_w_chan_t = logic,
Expand Down Expand Up @@ -66,7 +65,6 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(

cva6_icache_axi_wrapper #(
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg ),
.axi_req_t ( axi_req_t ),
.axi_rsp_t ( axi_rsp_t )
) i_cva6_icache_axi_wrapper (
Expand All @@ -90,7 +88,6 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
// Port 2: Store Unit
std_nbdcache #(
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg ),
.axi_req_t ( axi_req_t ),
.axi_rsp_t ( axi_rsp_t )
) i_nbdcache (
Expand Down
4 changes: 1 addition & 3 deletions core/cache_subsystem/std_nbdcache.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,6 @@

module std_nbdcache import std_cache_pkg::*; import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions
parameter type axi_req_t = logic,
parameter type axi_rsp_t = logic
)(
Expand Down Expand Up @@ -91,8 +90,7 @@ import std_cache_pkg::*;
generate
for (genvar i = 0; i < 3; i++) begin : master_ports
cache_ctrl #(
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg )
.CVA6Cfg ( CVA6Cfg )
) i_cache_ctrl (
.bypass_i ( ~enable_i ),
.busy_o ( busy [i] ),
Expand Down
8 changes: 2 additions & 6 deletions core/cache_subsystem/wt_cache_subsystem.sv
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Expand Up @@ -21,7 +21,6 @@

module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig, // contains cacheable regions
parameter int unsigned NumPorts = 3,
parameter type noc_req_t = logic,
parameter type noc_resp_t = logic
Expand Down Expand Up @@ -77,8 +76,7 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
cva6_icache #(
// use ID 0 for icache reads
.CVA6Cfg ( CVA6Cfg ),
.RdTxId ( 0 ),
.ArianeCfg ( ArianeCfg )
.RdTxId ( 0 )
) i_cva6_icache (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
Expand All @@ -105,8 +103,7 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
.CVA6Cfg ( CVA6Cfg ),
// use ID 1 for dcache reads and amos. note that the writebuffer
// uses all IDs up to DCACHE_MAX_TX-1 for write transactions.
.RdAmoTxId ( 1 ),
.ArianeCfg ( ArianeCfg )
.RdAmoTxId ( 1 )
) i_wt_dcache (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
Expand Down Expand Up @@ -137,7 +134,6 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
`ifdef PITON_ARIANE
wt_l15_adapter #(
.CVA6Cfg ( CVA6Cfg ),
.SwapEndianess ( ArianeCfg.SwapEndianess )
) i_adapter (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
Expand Down
12 changes: 3 additions & 9 deletions core/cache_subsystem/wt_dcache.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -18,9 +18,7 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter int unsigned NumPorts = 3, // number of miss ports
// ID to be used for read and AMO transactions.
// note that the write buffer uses all IDs up to DCACHE_MAX_TX-1 for write transactions
parameter logic [CACHE_ID_WIDTH-1:0] RdAmoTxId = 1,
// contains cacheable regions
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
parameter logic [CACHE_ID_WIDTH-1:0] RdAmoTxId = 1
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
Expand Down Expand Up @@ -113,7 +111,6 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #(

wt_dcache_missunit #(
.CVA6Cfg ( CVA6Cfg ),
.AxiCompliant ( ArianeCfg.AxiCompliant ),
.AmoTxId ( RdAmoTxId ),
.NumPorts ( NumPorts )
) i_wt_dcache_missunit (
Expand Down Expand Up @@ -175,8 +172,7 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #(

wt_dcache_ctrl #(
.CVA6Cfg ( CVA6Cfg ),
.RdTxId ( RdAmoTxId ),
.ArianeCfg ( ArianeCfg )
.RdTxId ( RdAmoTxId )
) i_wt_dcache_ctrl (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
Expand Down Expand Up @@ -220,8 +216,7 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #(
assign rd_prio[2] = 1'b0;

wt_dcache_wbuffer #(
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg )
.CVA6Cfg ( CVA6Cfg )
) i_wt_dcache_wbuffer (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
Expand Down Expand Up @@ -279,7 +274,6 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #(

wt_dcache_mem #(
.CVA6Cfg ( CVA6Cfg ),
.AxiCompliant ( ArianeCfg.AxiCompliant ),
.NumPorts ( NumPorts )
) i_wt_dcache_mem (
.clk_i ( clk_i ),
Expand Down
5 changes: 2 additions & 3 deletions core/cache_subsystem/wt_dcache_ctrl.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -15,8 +15,7 @@

module wt_dcache_ctrl import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 1, // ID to use for read transactions
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig // contains cacheable regions
parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 1
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
Expand Down Expand Up @@ -87,7 +86,7 @@ module wt_dcache_ctrl import ariane_pkg::*; import wt_cache_pkg::*; #(
assign miss_size_o = (miss_nc_o) ? data_size_q : 3'b111;

// noncacheable if request goes to I/O space, or if cache is disabled
assign miss_nc_o = (~cache_en_i) | (~ariane_pkg::is_inside_cacheable_regions(ArianeCfg, {{{64-DCACHE_TAG_WIDTH-DCACHE_INDEX_WIDTH}{1'b0}}, address_tag_q, {DCACHE_INDEX_WIDTH{1'b0}}}));
assign miss_nc_o = (~cache_en_i) | (~ariane_pkg::is_inside_cacheable_regions(CVA6Cfg, {{{64-DCACHE_TAG_WIDTH-DCACHE_INDEX_WIDTH}{1'b0}}, address_tag_q, {DCACHE_INDEX_WIDTH{1'b0}}}));


assign miss_we_o = '0;
Expand Down
5 changes: 2 additions & 3 deletions core/cache_subsystem/wt_dcache_mem.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,6 @@

module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter bit AxiCompliant = 1'b0, // set this to 1 when using in conjunction with AXI bus adapter
parameter int unsigned NumPorts = 3
) (
input logic clk_i,
Expand Down Expand Up @@ -256,12 +255,12 @@ module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #(
assign wbuffer_ruser = wbuffer_data_i[wbuffer_hit_idx].user;
assign wbuffer_be = (|wbuffer_hit_oh) ? wbuffer_data_i[wbuffer_hit_idx].valid : '0;

if (AxiCompliant) begin : gen_axi_off
if (CVA6Cfg.BusType == ariane_pkg::BUS_TYPE_AXI4_ATOP) begin : gen_axi_offset
// In case of an uncached read, return the desired XLEN-bit segment of the most recent AXI read
assign wr_cl_off = (wr_cl_nc_i) ? (CVA6Cfg.AxiDataWidth == riscv::XLEN) ? '0 :
wr_cl_off_i[AXI_OFFSET_WIDTH-1:riscv::XLEN_ALIGN_BYTES] :
wr_cl_off_i[DCACHE_OFFSET_WIDTH-1:riscv::XLEN_ALIGN_BYTES];
end else begin : gen_piton_off
end else begin : gen_piton_offset
assign wr_cl_off = wr_cl_off_i[DCACHE_OFFSET_WIDTH-1:3];
end

Expand Down
3 changes: 1 addition & 2 deletions core/cache_subsystem/wt_dcache_missunit.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,6 @@

module wt_dcache_missunit import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter bit AxiCompliant = 1'b0, // set this to 1 when using in conjunction with AXI bus adapter
parameter logic [CACHE_ID_WIDTH-1:0] AmoTxId = 1, // TX id to be used for AMOs
parameter int unsigned NumPorts = 3 // number of miss ports
) (
Expand Down Expand Up @@ -255,7 +254,7 @@ module wt_dcache_missunit import ariane_pkg::*; import wt_cache_pkg::*; #(
end

// note: openpiton returns a full cacheline!
if (AxiCompliant) begin : gen_axi_rtrn_mux
if (CVA6Cfg.BusType == ariane_pkg::BUS_TYPE_AXI4_ATOP) begin : gen_axi_rtrn_mux
if (CVA6Cfg.AxiDataWidth > 64) begin
assign amo_rtrn_mux = mem_rtrn_i.data[amo_req_i.operand_a[$clog2(CVA6Cfg.AxiDataWidth/8)-1:3]*64 +: 64];
end else begin
Expand Down
7 changes: 3 additions & 4 deletions core/cache_subsystem/wt_dcache_wbuffer.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -50,8 +50,7 @@


module wt_dcache_wbuffer import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig // contains cacheable regions
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
Expand Down Expand Up @@ -141,10 +140,10 @@ module wt_dcache_wbuffer import ariane_pkg::*; import wt_cache_pkg::*; #(
logic is_nc_miss;
logic is_ni;
assign miss_tag = miss_paddr_o[ariane_pkg::DCACHE_INDEX_WIDTH+:ariane_pkg::DCACHE_TAG_WIDTH];
assign is_nc_miss = !ariane_pkg::is_inside_cacheable_regions(ArianeCfg, {{64-DCACHE_TAG_WIDTH-DCACHE_INDEX_WIDTH{1'b0}}, miss_tag, {DCACHE_INDEX_WIDTH{1'b0}}});
assign is_nc_miss = !ariane_pkg::is_inside_cacheable_regions(CVA6Cfg, {{64-DCACHE_TAG_WIDTH-DCACHE_INDEX_WIDTH{1'b0}}, miss_tag, {DCACHE_INDEX_WIDTH{1'b0}}});
assign miss_nc_o = !cache_en_i || is_nc_miss;
// Non-idempotent if request goes to NI region
assign is_ni = ariane_pkg::is_inside_nonidempotent_regions(ArianeCfg, {{64-DCACHE_TAG_WIDTH-DCACHE_INDEX_WIDTH{1'b0}}, req_port_i.address_tag, {DCACHE_INDEX_WIDTH{1'b0}}});
assign is_ni = ariane_pkg::is_inside_nonidempotent_regions(CVA6Cfg, {{64-DCACHE_TAG_WIDTH-DCACHE_INDEX_WIDTH{1'b0}}, req_port_i.address_tag, {DCACHE_INDEX_WIDTH{1'b0}}});

assign miss_we_o = 1'b1;
assign miss_vld_bits_o = '0;
Expand Down
6 changes: 2 additions & 4 deletions core/cache_subsystem/wt_l15_adapter.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -50,8 +50,7 @@


module wt_l15_adapter import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter bit SwapEndianess = 1
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty
) (
input logic clk_i,
input logic rst_ni,
Expand Down Expand Up @@ -133,8 +132,7 @@ l15_rtrn_t rtrn_fifo_data;


// openpiton is big endian
if (SwapEndianess) assign l15_req_o.l15_data = swendian64(dcache_data.data);
else assign l15_req_o.l15_data = dcache_data.data;
assign l15_req_o.l15_data = swendian64(dcache_data.data);

// arbiter
rrarbiter #(
Expand Down
8 changes: 2 additions & 6 deletions core/cva6.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -106,7 +106,6 @@ module cva6 import ariane_pkg::*; #(
r_chan_t r;
},
//
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig,
parameter type acc_cfg_t = logic,
parameter acc_cfg_t AccCfg = '0,
parameter type cvxif_req_t = cvxif_pkg::cvxif_req_t,
Expand Down Expand Up @@ -527,8 +526,7 @@ module cva6 import ariane_pkg::*; #(
// ---------
ex_stage #(
.CVA6Cfg ( CVA6Cfg ),
.ASID_WIDTH ( ASID_WIDTH ),
.ArianeCfg ( ArianeCfg )
.ASID_WIDTH ( ASID_WIDTH )
) ex_stage_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
Expand Down Expand Up @@ -826,7 +824,6 @@ module cva6 import ariane_pkg::*; #(
// this is a cache subsystem that is compatible with OpenPiton
wt_cache_subsystem #(
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg ),
.NumPorts ( NumPorts ),
.noc_req_t ( noc_req_t ),
.noc_resp_t ( noc_resp_t )
Expand Down Expand Up @@ -871,7 +868,6 @@ module cva6 import ariane_pkg::*; #(
// not as important since this cache subsystem is about to be
// deprecated
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg ),
.axi_ar_chan_t ( axi_ar_chan_t ),
.axi_aw_chan_t ( axi_aw_chan_t ),
.axi_w_chan_t ( axi_w_chan_t ),
Expand Down Expand Up @@ -983,7 +979,7 @@ module cva6 import ariane_pkg::*; #(
// -------------------
// pragma translate_off
`ifndef VERILATOR
initial ariane_pkg::check_cfg(ArianeCfg, CVA6Cfg);
initial ariane_pkg::check_cfg(CVA6Cfg);
`endif
// pragma translate_on

Expand Down
6 changes: 2 additions & 4 deletions core/ex_stage.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -16,8 +16,7 @@

module ex_stage import ariane_pkg::*; #(
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::cva6_cfg_empty,
parameter int unsigned ASID_WIDTH = 1,
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
parameter int unsigned ASID_WIDTH = 1
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
Expand Down Expand Up @@ -302,8 +301,7 @@ module ex_stage import ariane_pkg::*; #(

load_store_unit #(
.CVA6Cfg ( CVA6Cfg ),
.ASID_WIDTH ( ASID_WIDTH ),
.ArianeCfg ( ArianeCfg )
.ASID_WIDTH ( ASID_WIDTH )
) lsu_i (
.clk_i,
.rst_ni,
Expand Down
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