Guillaume add-ons

core/commit_stage.sv

@@ -36,13 +36,13 @@ module commit_stage
     input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
     // Acknowledge that we are indeed committing - ISSUE_STAGE
     output logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_o,
-    // Register file write address - ID_STAGE
+    // Register file write address - ISSUE_STAGE
     output logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_o,
-    // Register file write data - ID_STAGE
+    // Register file write data - ISSUE_STAGE
     output logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_o,
-    // Register file write enable - ID_STAGE
+    // Register file write enable - ISSUE_STAGE
     output logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_o,
-    // Floating point register enable - ID_STAGE
+    // Floating point register enable - ISSUE_STAGE
     output logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_o,
     // Result of AMO operation - CACHE
     input amo_resp_t amo_resp_i,

core/ex_stage.sv

@@ -28,63 +28,63 @@ module ex_stage
     input logic flush_i,
     // TO_BE_COMPLETED - CSR_REGFILE
     input logic debug_mode_i,
-    // rs1 forwarding - ID_STAGE
+    // rs1 forwarding - ISSUE_STAGE
     input logic [riscv::VLEN-1:0] rs1_forwarding_i,
-    // rs2 forwarding - ID_STAGE
+    // rs2 forwarding - ISSUE_STAGE
     input logic [riscv::VLEN-1:0] rs2_forwarding_i,
-    // FU data useful to execute instruction - ID_STAGE
+    // FU data useful to execute instruction - ISSUE_STAGE
     input fu_data_t fu_data_i,
-    // PC of the current instruction - ID_STAGE
+    // PC of the current instruction - ISSUE_STAGE
     input logic [riscv::VLEN-1:0] pc_i,
-    // Report whether isntruction is compressed - ID_STAGE
+    // Report whether isntruction is compressed - ISSUE_STAGE
     input logic is_compressed_instr_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // TO_BE_COMPLETED - ISSUE_STAGE
     output riscv::xlen_t flu_result_o,
-    // ID of the scoreboard entry at which a=to write back - ID_STAGE
+    // ID of the scoreboard entry at which a=to write back - ISSUE_STAGE
     output logic [TRANS_ID_BITS-1:0] flu_trans_id_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // TO_BE_COMPLETED - ISSUE_STAGE
     output exception_t flu_exception_o,
-    // FLU is ready - ID_STAGE
+    // FLU is ready - ISSUE_STAGE
     output logic flu_ready_o,
-    // FLU result is valid - ID_STAGE
+    // FLU result is valid - ISSUE_STAGE
     output logic flu_valid_o,
-    // ALU result is valid - ID_STAGE
+    // ALU instruction is valid - ISSUE_STAGE
     input logic alu_valid_i,
-    // Branch unit result is valid - ID_STAGE
+    // Branch unit instruction is valid - ISSUE_STAGE
     input logic branch_valid_i,
-    // Information of branch prediction - ID_STAGE
+    // Information of branch prediction - ISSUE_STAGE
     input branchpredict_sbe_t branch_predict_i,
     // The branch engine uses the write back from the ALU - several_modules
     output bp_resolve_t resolved_branch_o,
-    // ID signaling that we resolved the branch - ID_STAGE
+    // Signaling that we resolved the branch - ISSUE_STAGE
     output logic resolve_branch_o,
-    // CSR result is valid - ID_STAGE
+    // CSR instruction is valid - ISSUE_STAGE
     input logic csr_valid_i,
-    // TO_BE_COMPLETED - CSR_REGISTERS
+    // CSR address to write - COMMIT_STAGE
     output logic [11:0] csr_addr_o,
     // TO_BE_COMPLETED - COMMIT_STAGE
     input logic csr_commit_i,
-    // MULT result is valid - ID_STAGE
+    // MULT instruction is valid - ISSUE_STAGE
     input logic mult_valid_i,
-    // FU is ready - ID_STAGE
+    // LSU is ready - ISSUE_STAGE
     output logic lsu_ready_o,
-    // LSU result is valid - ID_STAGE
+    // LSU instruction is valid - ISSUE_STAGE
     input logic lsu_valid_i,
-    // Load result is valid - ID_STAGE
+    // Load result is valid - ISSUE_STAGE
     output logic load_valid_o,
-    // Load result valid - ID_STAGE
+    // Load result valid - ISSUE_STAGE
     output riscv::xlen_t load_result_o,
-    // Load instruction ID - ID_STAGE
+    // Load instruction ID - ISSUE_STAGE
     output logic [TRANS_ID_BITS-1:0] load_trans_id_o,
-    // Exception generated by load instruction - ID_STAGE
+    // Exception generated by load instruction - ISSUE_STAGE
     output exception_t load_exception_o,
-    // Store result is valid - ID_STAGE
+    // Store result is valid - ISSUe_STAGE
     output logic store_valid_o,
-    // Store result - ID_STAGE
+    // Store result - ISSUE_STAGE
     output riscv::xlen_t store_result_o,
-    // Store instruction ID - ID_STAGE
+    // Store instruction ID - ISSUE_STAGE
     output logic [TRANS_ID_BITS-1:0] store_trans_id_o,
-    // Exception generated by store instruction - ID_STAGE
+    // Exception generated by store instruction - ISSUE_STAGE
     output exception_t store_exception_o,
     // TO_BE_COMPLETED - COMMIT_STAGE
     input logic lsu_commit_i,
@@ -98,45 +98,45 @@ module ex_stage
     output logic no_st_pending_o,
     // Atomic result is valid - COMMIT_STAGE
     input logic amo_valid_commit_i,
-    // FU is ready - ID_STAGE
+    // FU is ready - ISSUE_STAGE
     output logic fpu_ready_o,
-    // FPU result is ready - ID_STAGE
+    // FPU instruction is ready - ISSUE_STAGE
     input logic fpu_valid_i,
-    // FPU format - ID_STAGE
+    // FPU format - ISSUE_STAGE
     input logic [1:0] fpu_fmt_i,
-    // FPU rm - ID_STAGE
+    // FPU rm - ISSUE_STAGE
     input logic [2:0] fpu_rm_i,
-    // FPU frm - ID_STAGE
+    // FPU frm - ISSUE_STAGE
     input logic [2:0] fpu_frm_i,
     // FPU precision control - CSR_REGFILE
     input logic [6:0] fpu_prec_i,
-    // FPU transaction ID - ID_STAGE
+    // FPU transaction ID - ISSUE_STAGE
     output logic [TRANS_ID_BITS-1:0] fpu_trans_id_o,
-    // FPU result - ID_STAGE
+    // FPU result - ISSUE_STAGE
     output riscv::xlen_t fpu_result_o,
-    // FPU valid - ID_STAGE
+    // FPU valid - ISSUE_STAGE
     output logic fpu_valid_o,
-    // FPU exception - ID_STAGE
+    // FPU exception - ISSUE_STAGE
     output exception_t fpu_exception_o,
     // CVXIF instruction is valid - ISSUE_STAGE
     input logic x_valid_i,
     // CVXIF is ready - ISSUE_STAGE
     output logic x_ready_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // undecoded instruction - ISSUE_STAGE
     input logic [31:0] x_off_instr_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CVXIF transaction ID - ISSUE_STAGE
     output logic [TRANS_ID_BITS-1:0] x_trans_id_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CVXIF exception - ISSUE_STAGE
     output exception_t x_exception_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CVXIF result - ISSUE_STAGE
     output riscv::xlen_t x_result_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CVXIF result valid - ISSUE_STAGE
     output logic x_valid_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CVXIF write enable - ISSUE_STAGE
     output logic x_we_o,
-    // TO_BE_COMPLETED - SUBSYSTEM
+    // CVXIF request - SUBSYSTEM
     output cvxif_pkg::cvxif_req_t cvxif_req_o,
-    // TO_BE_COMPLETED - SUBSYSTEM
+    // CVXIF response - SUBSYSTEM
     input cvxif_pkg::cvxif_resp_t cvxif_resp_i,
     // accelerate port result is valid - ACC_DISPATCHER
     input logic acc_valid_i,