adding bitmanip and atomic arch-tests

verif/regress/install-riscv-arch-test.sh

@@ -17,7 +17,7 @@ fi
 if ! [ -n "$ARCH_TEST_REPO" ]; then
   ARCH_TEST_REPO=https://github.com/riscv-non-isa/riscv-arch-test
   ARCH_TEST_BRANCH=main
-  ARCH_TEST_HASH="46cf99d0e020887e398508fc776928a1adad7c23"
+  ARCH_TEST_HASH="a5a49fc9f244192649e57fe61b4513d9bc39b1e3"
 fi
 echo "Repo:  " $ARCH_TEST_REPO
 echo "Branch:" $ARCH_TEST_BRANCH

verif/sim/cva6.py

@@ -561,7 +561,7 @@ def run_c(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir,
          -nostartfiles %s \
          -I%s/dv/user_extension \
           -T%s %s -o %s " % \
-         (get_env_var("RISCV_GCC", debug_cmd = debug_cmd), c_test, cwd, 
+         (get_env_var("RISCV_GCC", debug_cmd = debug_cmd), c_test, cwd,
 					  linker, gcc_opts, elf))
   cmd += (" -march=%s" % isa)
   cmd += (" -mabi=%s" % mabi)
@@ -849,9 +849,9 @@ def load_config(args, cwd):
   Returns:
       Loaded configuration dictionary.
   """
-  
+
   global isa_extension_list
-  isa_extension_list = args.isa_extension.split(",")  
+  isa_extension_list = args.isa_extension.split(",")
   isa_extension_list.append("zicsr")
   isa_extension_list.append("zifencei")
 
@@ -882,13 +882,13 @@ def load_config(args, cwd):
       args.testlist = cwd + "/target/"+ args.target +"/testlist.yaml"
     if args.target == "cv64a6_imafdc_sv39":
       args.mabi = "lp64d"
-      args.isa  = "rv64gc"
+      args.isa  = "rv64gc_zba_zbb_zbs_zbc"
     elif args.target == "cv32a60x": # step1 configuration
       args.mabi = "ilp32"
-      args.isa  = "rv32imac"
+      args.isa  = "rv32imac_zba_zbb_zbs_zbc"
     elif args.target == "cv32a6_embedded":
       args.mabi = "ilp32"
-      args.isa  = "rv32imc"
+      args.isa  = "rv32imc_zba_zbb_zbs_zbc"
     elif args.target == "cv32a6_imac_sv0":
       args.mabi = "ilp32"
       args.isa  = "rv32imac"
@@ -1017,13 +1017,13 @@ def main():
     cfg = load_config(args, cwd)
     # Create output directory
     output_dir = create_output(args.o, args.noclean, cwd+"/out_")
-    
+
     #add z,s,x extensions to the isa if there are some
-    if isa_extension_list !=['']:	
+    if isa_extension_list !=['']:
       for i in isa_extension_list:
         if i!= "":
           args.isa += (f"_{i}")
-        
+
     if args.verilog_style_check:
       logging.debug("Run style check")
       style_err = run_cmd("verilog_style/run.sh")