Merge branch 'master' into fix_cache_line_width_64

openhwgroup · Dec 2, 2024 · 7d28ba9 · 7d28ba9
2 parents 43c9c3f + ba8ac71
commit 7d28ba9
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/core/cache_subsystem/wt_dcache_missunit.sv b/core/cache_subsystem/wt_dcache_missunit.sv
@@ -199,7 +199,7 @@ module wt_dcache_missunit
   // generate random cacheline index
   lfsr #(
       .LfsrWidth(8),
-      .OutWidth ($clog2(CVA6Cfg.DCACHE_SET_ASSOC))
+      .OutWidth (CVA6Cfg.DCACHE_SET_ASSOC_WIDTH)
   ) i_lfsr_inv (
       .clk_i (clk_i),
       .rst_ni(rst_ni),