linting

openhwgroup · Feb 19, 2024 · 7aacc52 · 7aacc52
1 parent 996be08
commit 7aacc52
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/core/mmu_unify/cva6_mmu.sv b/core/mmu_unify/cva6_mmu.sv
@@ -380,7 +380,7 @@ always_comb begin : instr_interface
   // an error.
   if ((|enable_translation_i[HYP_EXT:0])) begin
     // we work with SV39 or SV32, so if VM is enabled, check that all bits [riscv::VLEN-1:riscv::SV-1] are equal
-    if (icache_areq_i.fetch_req && !((&icache_areq_i.fetch_vaddr[riscv::VLEN-1:riscv::SV-1]) == 1'b1 || (|icache_areq_i.fetch_vaddr[riscv::VLEN-1:riscv::SV-1]) == 1'b0)) begin
+    if (icache_areq_i.fetch_req && !((&icache_areq_i.fetch_vaddr[riscv::VLEN-1:riscv::SV-1]) == 1'b1 || (|icache_areq_i.fetch_vaddr[riscv::VLEN-1:riscv::SV-1]) == 1'b0)) 
       if (HYP_EXT == 1)
         icache_areq_o.fetch_exception = {
           riscv::INSTR_ACCESS_FAULT,
@@ -394,7 +394,7 @@ always_comb begin : instr_interface
         icache_areq_o.fetch_exception = {
           riscv::INSTR_ACCESS_FAULT, {riscv::XLEN'(icache_areq_i.fetch_vaddr)}, 1'b1
         };
-    end
+
     icache_areq_o.fetch_valid = 1'b0;
     // ---------//
     // ITLB Hit