ariane_testharness/ariane_xilinx: Fix AXI ID width (#813)

- Fix the AXI ID width for the CLINT (previously `4`, now `5`) - Parametrise the CLINT's AXI types - Deprecate `axi_[master|slave]_connect` and move to AXI assign macros, as they allow arbitrary AXI types Signed-off-by: Nils Wistoff <[email protected]>
openhwgroup · Feb 6, 2022 · 741e821 · 741e821
1 parent da74358
commit 741e821
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diff --git a/Bender.yml b/Bender.yml
@@ -153,10 +153,6 @@ sources:
     - common/submodules/common_cells/src/stream_demux.sv
     - common/submodules/common_cells/src/stream_arbiter.sv
     - common/submodules/common_cells/src/stream_arbiter_flushable.sv
-    - common/local/util/axi_master_connect.sv
-    - common/local/util/axi_slave_connect.sv
-    - common/local/util/axi_master_connect_rev.sv
-    - common/local/util/axi_slave_connect_rev.sv
     - corev_apu/axi/src/axi_cut.sv
     - corev_apu/axi/src/axi_join.sv
     - corev_apu/axi/src/axi_delayer.sv

diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -70,10 +70,6 @@ src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv ==> core/fpu/src/fpu_div_s
  src/common_cells/src/stream_mux.sv                   ==> common/submodules/common_cells/src/stream_mux.sv
  src/common_cells/src/stream_demux.sv                 ==> common/submodules/common_cells/src/stream_demux.sv
  src/common_cells/src/exp_backoff.sv                  ==> common/submodules/common_cells/src/exp_backoff.sv
- src/util/axi_master_connect.sv                       ==> common/local/util/axi_master_connect.sv
- src/util/axi_slave_connect.sv                        ==> common/local/util/axi_slave_connect.sv
- src/util/axi_master_connect_rev.sv                   ==> common/local/util/axi_master_connect_rev.sv
- src/util/axi_slave_connect_rev.sv                    ==> common/local/util/axi_slave_connect_rev.sv
  src/axi/src/axi_cut.sv                               ==> corev_apu/axi/src/axi_cut.sv
  src/axi/src/axi_join.sv                              ==> corev_apu/axi/src/axi_join.sv
  src/axi/src/axi_delayer.sv                           ==> corev_apu/axi/src/axi_delayer.sv
@@ -107,6 +103,14 @@ src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv ==> core/fpu/src/fpu_div_s
  tb/common/SimJTAG.sv                                 ==> corev_apu/tb/common/SimJTAG.sv
 ```
 
+#### Removed standalone components
+```
+src/util/axi_master_connect.sv
+src/util/axi_slave_connect.sv
+src/util/axi_master_connect_rev.sv
+src/util/axi_slave_connect_rev.sv
+```
+
 ### 4.2.0 - 2019-06-04
 
 ### Added

diff --git a/Flist.ariane b/Flist.ariane
@@ -67,10 +67,6 @@ include/instr_tracer_pkg.sv
 src/util/instr_tracer_if.sv
 src/util/instr_tracer.sv
 src/util/sram.sv
-src/util/axi_master_connect.sv
-src/util/axi_master_connect_rev.sv
-src/util/axi_slave_connect.sv
-src/util/axi_slave_connect_rev.sv
 src/fpga-support/rtl/SyncSpRamBeNx64.sv
 src/dromajo_ram.sv
 src/axi_mem_if/src/axi2mem.sv

diff --git a/Makefile b/Makefile
@@ -196,10 +196,6 @@ src :=  $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv))
         common/submodules/common_cells/src/exp_backoff.sv                            \
         common/submodules/common_cells/src/addr_decode.sv                            \
         common/submodules/common_cells/src/stream_register.sv                        \
-        common/local/util/axi_master_connect.sv                                      \
-        common/local/util/axi_slave_connect.sv                                       \
-        common/local/util/axi_master_connect_rev.sv                                  \
-        common/local/util/axi_slave_connect_rev.sv                                   \
         corev_apu/axi/src/axi_cut.sv                                                 \
         corev_apu/axi/src/axi_join.sv                                                \
         corev_apu/axi/src/axi_delayer.sv                                             \

diff --git a/common/local/util/axi_master_connect.sv b/common/local/util/axi_master_connect.sv
diff --git a/common/local/util/axi_master_connect_rev.sv b/common/local/util/axi_master_connect_rev.sv
diff --git a/common/local/util/axi_slave_connect.sv b/common/local/util/axi_slave_connect.sv
diff --git a/common/local/util/axi_slave_connect_rev.sv b/common/local/util/axi_slave_connect_rev.sv
diff --git a/corev_apu/clint/axi_lite_interface.sv b/corev_apu/clint/axi_lite_interface.sv
@@ -16,13 +16,15 @@
 module axi_lite_interface #(
     parameter int unsigned AXI_ADDR_WIDTH = 64,
     parameter int unsigned AXI_DATA_WIDTH = 64,
-    parameter int unsigned AXI_ID_WIDTH   = 10
+    parameter int unsigned AXI_ID_WIDTH   = 10,
+    parameter type         axi_req_t      = ariane_axi::req_t,
+    parameter type         axi_resp_t     = ariane_axi::resp_t
 ) (
     input logic                               clk_i,    // Clock
     input logic                               rst_ni,   // Asynchronous reset active low
 
-    input  ariane_axi::req_t                  axi_req_i,
-    output ariane_axi::resp_t                 axi_resp_o,
+    input  axi_req_t                          axi_req_i,
+    output axi_resp_t                         axi_resp_o,
 
     output logic [AXI_ADDR_WIDTH-1:0]         address_o,
     output logic                              en_o,        // transaction is valid

diff --git a/corev_apu/clint/clint.sv b/corev_apu/clint/clint.sv
@@ -20,13 +20,15 @@ module clint #(
     parameter int unsigned AXI_ADDR_WIDTH = 64,
     parameter int unsigned AXI_DATA_WIDTH = 64,
     parameter int unsigned AXI_ID_WIDTH   = 10,
-    parameter int unsigned NR_CORES       = 1 // Number of cores therefore also the number of timecmp registers and timer interrupts
+    parameter int unsigned NR_CORES       = 1, // Number of cores therefore also the number of timecmp registers and timer interrupts
+    parameter type         axi_req_t      = ariane_axi::req_t,
+    parameter type         axi_resp_t     = ariane_axi::resp_t
 ) (
     input  logic                clk_i,       // Clock
     input  logic                rst_ni,      // Asynchronous reset active low
     input  logic                testmode_i,
-    input  ariane_axi::req_t    axi_req_i,
-    output ariane_axi::resp_t   axi_resp_o,
+    input  axi_req_t            axi_req_i,
+    output axi_resp_t           axi_resp_o,
     input  logic                rtc_i,       // Real-time clock in (usually 32.768 kHz)
     output logic [NR_CORES-1:0] timer_irq_o, // Timer interrupts
     output logic [NR_CORES-1:0] ipi_o        // software interrupt (a.k.a inter-process-interrupt)
@@ -63,7 +65,9 @@ module clint #(
     axi_lite_interface #(
         .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ),
         .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
-        .AXI_ID_WIDTH   ( AXI_ID_WIDTH    )
+        .AXI_ID_WIDTH   ( AXI_ID_WIDTH   ),
+        .axi_req_t      ( axi_req_t      ),
+        .axi_resp_t     ( axi_resp_t     )
     ) axi_lite_interface_i (
         .clk_i      ( clk_i      ),
         .rst_ni     ( rst_ni     ),