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UM: Part number + reshuffled Zb* RV32/RV64 instructions (#1733)
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@jquevremont
jquevremont authored Dec 21, 2023
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2 changes: 1 addition & 1 deletion docs/01_cva6_user/AXI_Interface.rst
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Expand Up @@ -24,8 +24,8 @@ In order to understand how the AXI memory interface behaves in CVA6, it is neces
:align: left
:header: "Configuration", "Implementation"

"CV32A60AX", "AXI included"
"CV32A60X", "AXI included"
"CV32A60MX", "AXI included"

About the AXI4 protocol
~~~~~~~~~~~~~~~~~~~~~~~
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4 changes: 2 additions & 2 deletions docs/01_cva6_user/CSR_Performance_Counters.rst
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Expand Up @@ -25,8 +25,8 @@
:align: left
:header: "Configuration", "Implementation"

"CV32A60X", "Performance counters included"
"CV32A60MX", "No performance counters"
"CV32A60AX", "Performance counters included"
"CV32A60X", "No performance counters"

CSR performance counters control
================================
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2 changes: 1 addition & 1 deletion docs/01_cva6_user/CVX_Interface_Coprocessor.rst
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Expand Up @@ -31,8 +31,8 @@ with external coprocessors.
:align: left
:header: "Configuration", "Implementation"

"CV32A60AX", "CV-X-IF included"
"CV32A60X", "CV-X-IF included"
"CV32A60MX", "CV-X-IF included"


CV-X-IF interface specification
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8 changes: 4 additions & 4 deletions docs/01_cva6_user/Interfaces.rst
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Expand Up @@ -32,8 +32,8 @@ The AXI interface is described in a separate chapter.
:align: left
:header: "Configuration", "Implementation"

"CV32A60AX", "AXI implemented"
"CV32A60X", "AXI implemented"
"CV32A60MX", "AXI implemented"

Debug Interface
---------------
Expand All @@ -50,8 +50,8 @@ Debug Interface
:align: left
:header: "Configuration", "Implementation"

"CV32A60X", "Debug interface implemented"
"CV32A60MX", "No debug interface"
"CV32A60AX", "Debug interface implemented"
"CV32A60X", "No debug interface"

Interrupt Interface
-------------------
Expand All @@ -75,5 +75,5 @@ For more information, refer to OpenPiton documents.
:align: left
:header: "Configuration", "Implementation"

"CV32A60AX", "No TRI interface"
"CV32A60X", "No TRI interface"
"CV32A60MX", "No TRI interface"
8 changes: 4 additions & 4 deletions docs/01_cva6_user/Introduction.rst
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Expand Up @@ -100,11 +100,11 @@ As of today, two configurations are being verified and addressed in this documen
:align: left
:header: "Configuration", "Short description", "Target", "Privilege levels", "Supported RISC-V ISA", "CV-X-IF"

"**CV32A60X**", "32-bit **application** core", "ASIC", "Machine, Supervisor, User", "RV32IMACZicsr_Zifencei_Zicount_Zba_Zbb_Zbc_Zbs_Zcb_Zicond", "Included"
"**CV32A60MX**", "32-bit **embedded** core", "ASIC", "Machine only", "RV32IMCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs_Zcb", "Included"
"**CV32A60AX**", "32-bit **application** core", "ASIC", "Machine, Supervisor, User", "RV32IMACZicsr_Zifencei_Zicount_Zba_Zbb_Zbc_Zbs_Zcb_Zicond", "Included"
"**CV32A60X**", "32-bit **embedded** core", "ASIC", "Machine only", "RV32IMCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs_Zcb", "Included"

CV32A60MX is an interim part number until the team can decide if this configuration is single- or dual-issue.
If the dual-issue architecture is selected, the part number will become CV32A65MX to denote the extra performance.
CV32A60X is an interim part number until the team can decide if this configuration is single- or dual-issue.
If the dual-issue architecture is selected, the part number will become CV32A65X to denote the extra performance.

In the future, dedicated user manuals for each configuration could be generated. The team is looking for a contributor to implement this through *templating*.

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98 changes: 50 additions & 48 deletions docs/01_cva6_user/Programmer_View.rst
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Expand Up @@ -32,23 +32,25 @@ CVA6 family
The following extensions are available for the CVA6 family.
Some of them are optional and are enabled through parameters in the SystemVerilog design.

**RV32** denotes RISC-V 32-bit extensions. **RV64** denotes RISC-V 64-bit extensions.

.. csv-table::
:widths: auto
:align: left
:header: "Extension", "Optional", "RV32 (in CV32A6)", "RV64 (in CV64A6)", "Note"

"I- Base Integer Instruction Set", "No", "✓", "✓", "Note 1"
"A - Atomic Instructions", "Yes", "✓", "✓", "Note 1"
"Zb* - Bit-Manipulation", "Yes", "✓", "✓", "Note 1"
"C - Compressed Instructions ", "Yes", "✓", "✓", "Note 1"
"Zcb - Code Size Reduction", "Yes", "✓", "✓", "Note 1"
"D - Double precision floating-point", "Yes", "", "✓", "Note 1"
"F - Single precision floating-point", "Yes", "✓", "✓", "Note 1"
"M - Integer Multiply/Divide", "No", "✓", "✓", "Note 1"
"Zicount - Performance Counters", "Yes", "✓", "✓", "Note 2"
"Zicsr - Control and Status Register Instructions", "No", "✓", "✓", "Note 2"
"Zifencei - Instruction-Fetch Fence", "No", "✓", "✓", "Note 2"
"Zicond - Integer Conditional Operations(Ratification pending)", "Yes", "✓", "✓", "Note 2"
"I- Base Integer Instruction Set", "No", "✔", "✔", "Note 1"
"A - Atomic Instructions", "Yes", "✔", "✔", "Note 1"
"Zb* - Bit-Manipulation", "Yes", "✔", "✔", "Note 1"
"C - Compressed Instructions ", "Yes", "✔", "✔", "Note 1"
"Zcb - Code Size Reduction", "Yes", "✔", "✔", "Note 1"
"D - Double precision floating-point", "Yes", "", "✔", "Note 1"
"F - Single precision floating-point", "Yes", "✔", "✔", "Note 1"
"M - Integer Multiply/Divide", "No", "✔", "✔", "Note 1"
"Zicount - Performance Counters", "Yes", "✔", "✔", "Note 2"
"Zicsr - Control and Status Register Instructions", "No", "✔", "✔", "Note 2"
"Zifencei - Instruction-Fetch Fence", "No", "✔", "✔", "Note 2"
"Zicond - Integer Conditional Operations(Ratification pending)", "Yes", "✔", "✔", "Note 2"

Notes:

Expand All @@ -57,50 +59,50 @@ Notes:

*The following tables detail the availability of extensions for the various CVA6 configurations:*

CV32A60X extensions
CV32A60AX extensions
~~~~~~~~~~~~~~~~~~~

These extensions are available in CV32A60X:
These extensions are available in CV32A60AX:

.. csv-table::
:widths: auto
:align: left
:header: "Extension", "Available in CV32A60X"
:header: "Extension", "Available in CV32A60AX"

"RV32I - Base Integer Instruction Set", "✓"
"RV32A - Atomic Instructions", "✓"
"RV32Zb* - Bit-Manipulation (Zba, Zbb, Zbc, Zbs)", "✓"
"RV32C - Compressed Instructions ", "✓"
"RV32Zcb - Code Size Reduction", "✓"
"RV32I - Base Integer Instruction Set", "✔"
"RV32A - Atomic Instructions", "✔"
"RV32Zb* - Bit-Manipulation (Zba, Zbb, Zbc, Zbs)", "✔"
"RV32C - Compressed Instructions ", "✔"
"RV32Zcb - Code Size Reduction", "✔"
"RV32D - Double precision floating-point", ""
"RV32F - Single precision floating-point", ""
"RV32M - Integer Multiply/Divide", "✓"
"RVZicount - Performance Counters", "✓"
"RVZicsr - Control and Status Register Instructions", "✓"
"RVZifencei - Instruction-Fetch Fence", "✓"
"RVZicond - Integer Conditional Operations(Ratification pending)", "✓"
"RV32M - Integer Multiply/Divide", "✔"
"RVZicount - Performance Counters", "✔"
"RVZicsr - Control and Status Register Instructions", "✔"
"RVZifencei - Instruction-Fetch Fence", "✔"
"RVZicond - Integer Conditional Operations(Ratification pending)", "✔"

CV32A60MX extensions
CV32A60X extensions
~~~~~~~~~~~~~~~~~~~

These extensions are available in CV32A60MX:
These extensions are available in CV32A60X:

.. csv-table::
:widths: auto
:align: left
:header: "Extension", "Available in CV32A60X"
:header: "Extension", "Available in CV32A60AX"

"RV32I - Base Integer Instruction Set", "✓"
"RV32I - Base Integer Instruction Set", "✔"
"RV32A - Atomic Instructions", ""
"RV32Zb* - Bit-Manipulation (Zba, Zbb, Zbc, Zbs)", "✓"
"RV32C - Compressed Instructions ", "✓"
"RV32Zcb - Code Size Reduction", "✓"
"RV32Zb* - Bit-Manipulation (Zba, Zbb, Zbc, Zbs)", "✔"
"RV32C - Compressed Instructions ", "✔"
"RV32Zcb - Code Size Reduction", "✔"
"RV32D - Double precision floating-point", ""
"RV32F - Single precision floating-point", ""
"RV32M - Integer Multiply/Divide", "✓"
"RV32M - Integer Multiply/Divide", "✔"
"RVZicount - Performance Counters", ""
"RVZicsr - Control and Status Register Instructions", "✓"
"RVZifencei - Instruction-Fetch Fence", "✓"
"RVZicsr - Control and Status Register Instructions", "✔"
"RVZifencei - Instruction-Fetch Fence", "✔"
"RVZicond - Integer Conditional Operations(Ratification pending)", ""


Expand All @@ -125,31 +127,31 @@ Note: The addition of the H Extension is in the process. After that, HS, VS, and

*The following tables detail the availability of privileges modes for the various CVA6 configurations:*

CV32A60X privilege modes
CV32A60AX privilege modes
~~~~~~~~~~~~~~~~~~~~~~~~

These privilege modes are available in CV32A60X:
These privilege modes are available in CV32A60AX:

.. csv-table::
:widths: auto
:align: left
:header: "Privileges", "Available in CV32A60X"
:header: "Privileges", "Available in CV32A60AX"

"M - Machine", "✓"
"S - Supervior", "✓"
"U - User", "✓"
"M - Machine", "✔"
"S - Supervior", "✔"
"U - User", "✔"

CV32A60MX privilege modes
CV32A60X privilege modes
~~~~~~~~~~~~~~~~~~~~~~~~

These privilege modes are available in CV32A60MX:
These privilege modes are available in CV32A60X:

.. csv-table::
:widths: auto
:align: left
:header: "Privileges", "Available in CV32A60MX"
:header: "Privileges", "Available in CV32A60X"

"M - Machine", "✓"
"M - Machine", "✔"
"S - Supervior", ""
"U - User", ""

Expand Down Expand Up @@ -178,13 +180,13 @@ Notes for the integrator:

*These are the addressing modes supported by the various CVA6 configurations:*

CV32A60X virtual memory
CV32A60AX virtual memory
~~~~~~~~~~~~~~~~~~~~~~~

CV32A60X integrates an MMU and supports both the **Bare** and **Sv32** addressing modes.
CV32A60AX integrates an MMU and supports both the **Bare** and **Sv32** addressing modes.


CV32A60MX virtual memory
CV32A60X virtual memory
~~~~~~~~~~~~~~~~~~~~~~~~

CV32A60X integrates no MMU and only supports the **Bare** addressing mode.
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4 changes: 4 additions & 0 deletions docs/01_cva6_user/RISCV_Instructions.rst
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Expand Up @@ -31,6 +31,10 @@ In the next pages, the ISA (Instruction Set Architecture) for various CVA6 confi
* RV32M – Standard Extension for Integer Multiplication and Division Instructions
* RV32A – Standard Extension for Atomic Instructions
* RV32C – Standard Extension for Compressed Instructions
* RVZba - Standard Extension for Bit Manipulation: Address generation instructions (RV32 and RV64)
* RVZbb - Standard Extension for Bit Manipulation: Basic bit manipulation (RV32 and RV64)
* RVZbc - Standard Extension for Bit Manipulation: Carry-less multiplication (RV32 and RV64)
* RVZbs - Standard Extension for Bit Manipulation: Single-bit instructions (RV32 and RV64)
* RV32Zcb – Standard Extension for Code Size Reduction
* RVZicsr – Standard Extension for CSR Instructions
* RVZifencei – Standard Extension for Instruction-Fetch Fence
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4 changes: 2 additions & 2 deletions docs/01_cva6_user/RISCV_Instructions_RV32A.rst
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Expand Up @@ -25,8 +25,8 @@
:align: left
:header: "Configuration", "Implementation"

"CV32A60X", "Implemented extension"
"CV32A60MX", "Not implemented extension"
"CV32A60AX", "Implemented extension"
"CV32A60X", "Not implemented extension"

**Note**: This chapter is specific to CV32A6 configurations. CV64A6 configurations implement as an option RV64A, that includes additional instructions.

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2 changes: 1 addition & 1 deletion docs/01_cva6_user/RISCV_Instructions_RV32C.rst
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Expand Up @@ -25,8 +25,8 @@
:align: left
:header: "Configuration", "Implementation"

"CV32A60AX", "Implemented extension"
"CV32A60X", "Implemented extension"
"CV32A60MX", "Implemented extension"

**Note**: This chapter is specific to CV32A6 configurations. CV64A6 configurations implement as an option RV64C, that includes a different list of instructions.

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2 changes: 1 addition & 1 deletion docs/01_cva6_user/RISCV_Instructions_RV32I.rst
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Expand Up @@ -27,8 +27,8 @@ This chapter is applicable to all CV32A6 configurations.
:align: left
:header: "Configuration", "Implementation"

"CV32A60AX", "Implemented extension"
"CV32A60X", "Implemented extension"
"CV32A60MX", "Implemented extension"

**Note**: CV64A6 implements RV64I that includes additional instructions.

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2 changes: 1 addition & 1 deletion docs/01_cva6_user/RISCV_Instructions_RV32M.rst
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Expand Up @@ -27,8 +27,8 @@ This chapter is applicable to all CV32A6 configurations.
:align: left
:header: "Configuration", "Implementation"

"CV32A60AX", "Implemented extension"
"CV32A60X", "Implemented extension"
"CV32A60MX", "Implemented extension"

**Note**: CV64A6 implements RV64M that includes additional instructions.

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2 changes: 1 addition & 1 deletion docs/01_cva6_user/RISCV_Instructions_RV32ZCb.rst
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Expand Up @@ -25,8 +25,8 @@
:align: left
:header: "Configuration", "Implementation"

"CV32A60AX", "Implemented extension"
"CV32A60X", "Implemented extension"
"CV32A60MX", "Implemented extension"

**Note**: This chapter is specific to CV32A6 configurations. CV64A6 configurations implement as an option RV64Zcb, that includes one additional instruction.

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