Updated user manual to address several configuration (second pass) (#…

…1696)
openhwgroup · Dec 13, 2023 · 6e41bc8 · 6e41bc8
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diff --git a/docs/01_cva6_user/CSR_Performance_Counters.rst b/docs/01_cva6_user/CSR_Performance_Counters.rst
@@ -18,6 +18,16 @@
 
 .. _cva6_csr_performance_counters:
 
+*Applicability of this chapter to configurations:*
+
+.. csv-table::
+   :widths: auto
+   :align: left
+   :header: "Configuration", "Implementation"
+
+   "CV32A60X", "Performance counters included"
+   "CV32E6?X", "No performance counters"
+
 CSR performance counters control
 ================================
 CVA6 implements performance counters according to the RISC-V Privileged Specification, version 1.11 (see Hardware Performance Monitor, Section 3.1.10). The performance counters are placed inside the Control and Status Registers(CSRs) and can be accessed with the ``CSRRW(I)`` and ``CSRRS/C(I)`` instructions.

diff --git a/docs/01_cva6_user/Core_Integration.rst b/docs/01_cva6_user/Core_Integration.rst
@@ -47,7 +47,6 @@ Suggested content:
 FPGA specific guidelines
 ------------------------
 Also needed for prototyping of ASICs
-
 Suggested content:
 
 * Typical critical paths in FPGA and suggestions for optimizations