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kasun-buddhi committed Sep 27, 2024
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2 changes: 1 addition & 1 deletion core/cache_subsystem/hpdcache
Submodule hpdcache updated 76 files
+0 −27 .github/workflows/verible_lint.yml
+0 −25 CHANGELOG.md
+5 −7 README.md
+0 −97 docs/LICENSE
+0 −20 docs/Makefile
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+0 −0 docs/hpdcache_spec_document/supplement/download_wavedrom.sh
+0 −0 docs/hpdcache_spec_document/version
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+8 −17 rtl/src/common/hpdcache_fifo_reg.sv
+9 −6 rtl/src/hpdcache_memctrl.sv
+1 −1 rtl/src/hpdcache_miss_handler.sv
+2 −2 rtl/src/hpdcache_mshr.sv
+1 −1 rtl/src/utils/hpdcache_mem_to_axi_read.sv
+1 −1 rtl/src/utils/hpdcache_mem_to_axi_write.sv
3 changes: 2 additions & 1 deletion ...include/cv32a60x_config_pkg_deprecated.sv → core/include/cv32a60x_config_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,7 @@ package cva6_config_pkg;
localparam CVA6ConfigNrStorePipeRegs = 0;
localparam CVA6ConfigNrLoadBufEntries = 2;

localparam CVA6ConfigRASDepth = 0;
localparam CVA6ConfigRASDepth = 2;
localparam CVA6ConfigBTBEntries = 0;
localparam CVA6ConfigBHTEntries = 0;

Expand All @@ -78,6 +78,7 @@ package cva6_config_pkg;
XLEN: unsigned'(CVA6ConfigXlen),
FpgaEn: bit'(CVA6ConfigFpgaEn),
TechnoCut: bit'(0),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
Expand Down
1 change: 1 addition & 0 deletions ve
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@@ -0,0 +1 @@
bash: -08-29/questa-uvm_sim/hello_world.cv32a60x.log: No such file or directory
1 change: 1 addition & 0 deletions veri
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@@ -0,0 +1 @@
bash: -08-28/questa-uvm_sim/hello_world.cv32a60x.log: No such file or directory
2 changes: 1 addition & 1 deletion verif/core-v-verif
Submodule core-v-verif updated 39 files
+15 −15 lib/cv_dv_utils/uvm/reset_gen/reset_driver_c.svh
+10 −5 lib/uvm_agents/uvma_axi/src/comps/uvma_axi_vseq.sv
+9 −5 lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_covg.sv
+5 −3 lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_drv.sv
+7 −2 lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_mon.sv
+3 −3 lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_vseq.sv
+1 −1 lib/uvm_agents/uvma_axi5/src/obj/pure_agent_cfg.sv
+2 −0 lib/uvm_agents/uvma_axi5/src/obj/uvma_axi_cntxt.sv
+2 −1 lib/uvm_agents/uvma_axi5/src/seq/uvma_axi_fw_preload_seq.sv
+5 −4 lib/uvm_agents/uvma_axi5/src/seq/uvma_axi_slv_seq.sv
+2 −2 lib/uvm_agents/uvma_axi5/src/seq/uvma_axi_transaction.sv
+46 −0 lib/uvm_agents/uvma_axi5/src/uvma_axi_assert.sv
+74 −74 lib/uvm_agents/uvma_axi5/src/uvma_axi_intf.sv
+29 −29 lib/uvm_agents/uvma_clknrst/uvma_clknrst_drv.sv
+16 −16 lib/uvm_agents/uvma_clknrst/uvma_clknrst_if.sv
+6 −10 lib/uvm_components/uvmc_rvfi_reference_model/rvfi_spike.sv
+0 −3 mk/Common.mk
+0 −1 mk/uvmt/vcs.mk
+0 −27 vendor/patches/riscv/riscv-isa-sim/0030-fix-csr-injection.patch
+0 −988 vendor/patches/riscv/riscv-isa-sim/0031-csr-refactor-params.patch
+0 −48 vendor/patches/riscv/riscv-isa-sim/0032-csr-injection-no-trap.patch
+0 −59 vendor/patches/riscv/riscv-isa-sim/0033-csr-injection-sign-extension.patch
+0 −153 vendor/patches/riscv/riscv-isa-sim/0034-0-interrupt-clearing-vars.patch
+5 −5 vendor/riscv/riscv-isa-sim/Makefile.in
+0 −2 vendor/riscv/riscv-isa-sim/arch_test_target/spike/link.ld
+66 −69 vendor/riscv/riscv-isa-sim/arch_test_target/spike/model_test.h
+90 −131 vendor/riscv/riscv-isa-sim/riscv/Proc.cc
+3 −6 vendor/riscv/riscv-isa-sim/riscv/Proc.h
+2 −10 vendor/riscv/riscv-isa-sim/riscv/Simulation.cc
+0 −2 vendor/riscv/riscv-isa-sim/riscv/Simulation.h
+7 −15 vendor/riscv/riscv-isa-sim/riscv/YamlParamSetter.cc
+7 −319 vendor/riscv/riscv-isa-sim/riscv/csrs_ext.cc
+1 −17 vendor/riscv/riscv-isa-sim/riscv/csrs_ext.h
+1 −2 vendor/riscv/riscv-isa-sim/riscv/processor.cc
+0 −16 vendor/riscv/riscv-isa-sim/riscv/riscv_dpi.cc
+0 −3 vendor/riscv/riscv-isa-sim/riscv/sim.cc
+2 −2 vendor/riscv/riscv-isa-sim/riscv/sim.h
+4 −9 vendor/riscv/riscv-isa-sim/spike_main/spike-dpi.cc
+0 −1 vendor/riscv/riscv-isa-sim/spike_main/spike_main.mk.in
5 changes: 4 additions & 1 deletion verif/env/uvme/cov/uvme_axi_ext_covg.sv
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Expand Up @@ -191,7 +191,7 @@ endclass : uvme_axi_ext_covg_c
function uvme_axi_ext_covg_c::new(string name="uvme_axi_ext_covg", uvm_component parent=null);

super.new(name, parent);

$display("uvme_axi_ext_covg_c is running here");
endfunction : new

function void uvme_axi_ext_covg_c::build_phase(uvm_phase phase);
Expand Down Expand Up @@ -243,6 +243,8 @@ endtask : run_phase
task uvme_axi_ext_covg_c::get_aw_item();

uvma_axi_transaction_c aw_item;
$display("get_aw_item started");
$display("uvme_axi_cov_aw_req_fifo : %p",uvme_axi_cov_aw_req_fifo.size());
uvme_axi_cov_aw_req_fifo.get(aw_item);
`uvm_info(get_type_name(), $sformatf("WRITE REQ ITEM DETECTED"), UVM_HIGH)
aw_trs_fifo = new [aw_trs_fifo.size()+1] (aw_trs_fifo);
Expand All @@ -265,6 +267,7 @@ endtask : get_ar_item
task uvme_axi_ext_covg_c::get_b_item();

uvma_axi_transaction_c b_item;
$display("get_b_item started");
uvme_axi_cov_b_resp_fifo.get(b_item);
`uvm_info(get_type_name(), $sformatf("WRITE RESP ITEM DETECTED"), UVM_HIGH)
foreach(aw_trs_fifo[i]) begin
Expand Down
2 changes: 1 addition & 1 deletion verif/env/uvme/uvme_cva6_cfg.sv
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Expand Up @@ -33,7 +33,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;

rand bit scoreboard_enabled;
rand bit tandem_enabled;
rand bit cov_model_enabled;
rand bit cov_model_enabled ; //Temp edit
rand bit trn_log_enabled;
rand int unsigned sys_clk_period;

Expand Down
1 change: 1 addition & 0 deletions verif/env/uvme/uvme_cva6_env.sv
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Expand Up @@ -374,6 +374,7 @@ task uvme_cva6_env_c::run_phase(uvm_phase phase);
begin
if(cfg.axi_cfg.is_active == UVM_ACTIVE) begin
uvma_axi_vseq_c axi_vseq;
$display("axi_vseq start");
axi_vseq = uvma_axi_vseq_c::type_id::create("axi_vseq");
axi_vseq.start(axi_agent.vsequencer);
end
Expand Down
2 changes: 1 addition & 1 deletion verif/env/uvme/uvme_cva6_pkg.sv
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Expand Up @@ -57,7 +57,7 @@ package uvme_cva6_pkg;

import "DPI-C" function void read_elf(input string filename);
import "DPI-C" function byte get_section(output longint address, output longint len);
import "DPI-C" context function void read_section_sv(input longint address, inout byte buffer[]);
import "DPI-C" context function void read_section_sv(input longint address, inout byte buffer[]);

// Default legal opcode and funct7 for RV32I instructions
bit [6:0] legal_i_opcode[$] = '{7'b0000011,
Expand Down
2 changes: 1 addition & 1 deletion verif/env/uvme/uvme_cva6_sb.sv
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Expand Up @@ -323,7 +323,7 @@ endfunction : check_mepc
function bit [XLEN:0] uvme_cva6_sb_c::check_mcycle_h(uvma_isacov_instr_c instr, uvma_isacov_instr_c instr_prev, int cycle_count);

// Check mcycle value after a CSR read
if (instr_prev == null) return;
if (instr_prev == null) return 32'd0; // ToDo: Temp fix

write_in_mcycle = (instr_prev.is_csr_write() && instr_prev.csr_val == 12'hb00) ? 1 : 0;
if (cfg.xlen == 32) begin
Expand Down
3 changes: 3 additions & 0 deletions verif/env/uvme/vseq/uvme_axi_fw_preload_seq.sv
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Expand Up @@ -48,8 +48,11 @@ task uvme_axi_fw_preload_seq_c::body();

void'(uvcl.get_arg_value("+elf_file=", binary));


if (binary != "") begin
$display("binary string 001: %s",binary);
read_elf(binary);
$display("binary string: %s",binary);
wait(p_sequencer.cntxt.axi_vi.clk);
// while there are more sections to process
while (get_section(address, len)) begin
Expand Down
1 change: 1 addition & 0 deletions verif/regress/verif/tests/riscv-compliance
Submodule riscv-compliance added at 220e78
15 changes: 11 additions & 4 deletions verif/sim/Makefile
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Expand Up @@ -357,12 +357,19 @@ questa_uvm_run:
@echo "[QUESTA] Running Model"
vsim -64 \
$(COMMON_RUN_UVM_FLAGS) \
-sv_lib $(SPIKE_INSTALL_DIR)/lib/libyaml-cpp \
-sv_lib $(SPIKE_INSTALL_DIR)/lib/libriscv \
-sv_lib $(SPIKE_INSTALL_DIR)/lib/libfesvr \
-sv_lib $(SPIKE_INSTALL_DIR)/lib/libdisasm \
-sv_lib $(QUESTASIM_HOME)/uvm-1.2/linux_x86_64/uvm_dpi \
-c -do "run -all; " \
-work $(VSIM_WORK_DIR) -t 1ns \
-suppress vsim-8451 \
-suppress 3829 -suppress vsim-8386\
-c -do "add wave -position insertpoint sim:/uvmt_cva6_tb/cva6_dut_wrap/cva6_tb_wrapper_i/i_cva6/gen_cache_wt/i_cache_subsystem/i_adapter/*" \
-do "run -all; " \
-work $(VSIM_WORK_DIR) -t 1ns \
-suppress vsim-8451 \
-suppress 3829 -suppress vsim-8386\
+permissive \
+elf_file=$(elf) \
+UVM_TESTNAME=uvmt_cva6_firmware_test_c \
-sv_seed 0 \
$(cov-run-opt) $(issrun_opts) \
+define+UNSUPPORTED_WITH+ \
Expand Down
4 changes: 2 additions & 2 deletions verif/sim/cva6.py
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Expand Up @@ -1174,8 +1174,8 @@ def check_spike_version():

logging.info(f"Spike Version: {user_spike_stderr_string}")

if user_spike_stderr_string != spike_version:
incorrect_version_exit("Spike", user_spike_stderr_string, spike_version)
#if user_spike_stderr_string != spike_version:
# incorrect_version_exit("Spike", user_spike_stderr_string, spike_version)


def check_verilator_version():
Expand Down
2 changes: 1 addition & 1 deletion verif/tb/uvmt/cva6_tb_wrapper.sv
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Expand Up @@ -37,7 +37,7 @@ import uvm_pkg::*;
import "DPI-C" function void read_elf(input string filename);
import "DPI-C" function byte read_symbol(input string symbol_name, inout longint unsigned address);
import "DPI-C" function byte get_section(output longint address, output longint len);
import "DPI-C" context function read_section_sv(input longint address, inout byte buffer[]);
import "DPI-C" context function void read_section_sv(input longint address, inout byte buffer[]); // ToDo: Temp fix
`endif

module cva6_tb_wrapper import uvmt_cva6_pkg::*; #(
Expand Down
50 changes: 29 additions & 21 deletions verif/tb/uvmt/uvmt_cva6_macros.sv
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Expand Up @@ -19,34 +19,42 @@
`ifndef __UVMT_CVA6_MACROS_SV__
`define __UVMT_CVA6_MACROS_SV__



//#####################################################################################################################################
//Temp edit
//#####################################################################################################################################

// Assign for RVFI CSR interface
`define RVFI_CSR_ASSIGN(csr_name) \
uvma_rvfi_csr_if#(uvme_cva6_pkg::XLEN) rvfi_csr_``csr_name``_if [RVFI_NRET-1:0](); \
for (genvar i = 0; i < RVFI_NRET; i++) begin \
assign rvfi_csr_``csr_name``_if[i].clk = clknrst_if.clk; \
assign rvfi_csr_``csr_name``_if[i].reset_n = clknrst_if.reset_n; \
assign rvfi_csr_``csr_name``_if[i].rvfi_csr_rmask = rvfi_if.rvfi_csr_o.``csr_name``.rmask; \
assign rvfi_csr_``csr_name``_if[i].rvfi_csr_wmask = rvfi_if.rvfi_csr_o.``csr_name``.wmask; \
assign rvfi_csr_``csr_name``_if[i].rvfi_csr_rdata = rvfi_if.rvfi_csr_o.``csr_name``.rdata; \
assign rvfi_csr_``csr_name``_if[i].rvfi_csr_wdata = rvfi_if.rvfi_csr_o.``csr_name``.wdata; \
for (genvar i = 0; i < RVFI_NRET; i++) begin : rvfi_csr_if_blk_``csr_name``\
uvma_rvfi_csr_if#(uvme_cva6_pkg::XLEN) rvfi_csr_``csr_name``_if (\
.clk ( clknrst_if.clk ), \
.reset_n ( clknrst_if.reset_n ),\
.rvfi_csr_rmask ( rvfi_if.rvfi_csr_o.``csr_name``.rmask ),\
.rvfi_csr_wmask ( rvfi_if.rvfi_csr_o.``csr_name``.wmask ),\
.rvfi_csr_rdata ( rvfi_if.rvfi_csr_o.``csr_name``.rdata ),\
.rvfi_csr_wdata ( rvfi_if.rvfi_csr_o.``csr_name``.wdata ) \
);\
end \

`define RVFI_CSR_SUFFIX_ASSIGN(csr_name, idx) \
uvma_rvfi_csr_if#(uvme_cva6_pkg::XLEN) rvfi_csr_``csr_name````idx``_if [RVFI_NRET-1:0](); \
for (genvar i = 0; i < RVFI_NRET; i++) begin \
assign rvfi_csr_``csr_name````idx``_if[i].clk = clknrst_if.clk; \
assign rvfi_csr_``csr_name````idx``_if[i].reset_n = clknrst_if.reset_n; \
assign rvfi_csr_``csr_name````idx``_if[i].rvfi_csr_rmask = rvfi_if.rvfi_csr_o.``csr_name``[``idx``].rmask; \
assign rvfi_csr_``csr_name````idx``_if[i].rvfi_csr_wmask = rvfi_if.rvfi_csr_o.``csr_name``[``idx``].wmask; \
assign rvfi_csr_``csr_name````idx``_if[i].rvfi_csr_rdata = rvfi_if.rvfi_csr_o.``csr_name``[``idx``].rdata; \
assign rvfi_csr_``csr_name````idx``_if[i].rvfi_csr_wdata = rvfi_if.rvfi_csr_o.``csr_name``[``idx``].wdata; \
for (genvar i = 0; i < RVFI_NRET; i++) begin : rvfi_csr_if_blk_``csr_name````idx`` \
uvma_rvfi_csr_if#(uvme_cva6_pkg::XLEN) rvfi_csr_``csr_name````idx``_if (\
.clk (clknrst_if.clk), \
.reset_n (clknrst_if.reset_n), \
.rvfi_csr_rmask (rvfi_if.rvfi_csr_o.``csr_name``[``idx``].rmask), \
.rvfi_csr_wmask (rvfi_if.rvfi_csr_o.``csr_name``[``idx``].wmask), \
.rvfi_csr_rdata (rvfi_if.rvfi_csr_o.``csr_name``[``idx``].rdata), \
.rvfi_csr_wdata (rvfi_if.rvfi_csr_o.``csr_name``[``idx``].wdata) \
); \
end \

// Create uvm_config_db::set call for a CSR interface
`define RVFI_CSR_UVM_CONFIG_DB_SET(csr_name, idx) \
uvm_config_db#(virtual uvma_rvfi_csr_if)::set(.cntxt(null), \
.inst_name("*"), \
.field_name({"csr_", `"csr_name`", "_vif", $sformatf("%0d", ``idx``)}), \
.value(rvfi_csr_``csr_name``_if[``idx``])); \

uvm_config_db#(virtual uvma_rvfi_csr_if)::set(.cntxt(null), \
.inst_name("*"), \
.field_name({"csr_", `"csr_name`", "_vif", $sformatf("%0d", ``idx``)}), \
.value(rvfi_csr_if_blk_``csr_name``[``idx``].rvfi_csr_``csr_name``_if)); \
`endif // __UVMT_CVA6_MACROS_SV__
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