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add csr in rvfi
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@yanicasa
yanicasa committed Feb 20, 2024
1 parent 6e8e265 commit 6c9e271
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Showing 12 changed files with 772 additions and 264 deletions.
437 changes: 363 additions & 74 deletions core/csr_regfile.sv
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91 changes: 37 additions & 54 deletions core/cva6.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -18,30 +18,11 @@ module cva6
#(
// CVA6 config
parameter config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg,
parameter bit IsRVFI = bit'(cva6_config_pkg::CVA6ConfigRvfiTrace),
// RVFI

parameter type rvfi_probes_t = struct packed {
logic [TRANS_ID_BITS-1:0] issue_pointer;
logic [CVA6Cfg.NrCommitPorts-1:0][TRANS_ID_BITS-1:0] commit_pointer;
logic flush_unissued_instr;
logic decoded_instr_valid;
logic flush;
logic decoded_instr_ack;
logic issue_instr_ack;
logic fetch_entry_valid;
logic [31:0] instruction;
logic is_compressed;
riscv::xlen_t rs1_forwarding;
riscv::xlen_t rs2_forwarding;
scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr;
exception_t ex_commit;
riscv::priv_lvl_t priv_lvl;
lsu_ctrl_t lsu_ctrl;
logic [((CVA6Cfg.CvxifEn || CVA6Cfg.RVV) ? 5 : 4)-1:0][riscv::XLEN-1:0] wbdata;
logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack;
logic [riscv::PLEN-1:0] mem_paddr;
logic debug_mode;
logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata;
logic csr;
logic scoreboard;
logic instr;
},

// AXI types
Expand Down Expand Up @@ -462,8 +443,7 @@ module cva6
lsu_ctrl_t rvfi_lsu_ctrl;
logic [riscv::PLEN-1:0] rvfi_mem_paddr;
logic rvfi_is_compressed;
rvfi_probes_t rvfi_probes;

rvfi_csr_t rvfi_csr;

// Accelerator port
logic [ 63:0] inval_addr;
Expand Down Expand Up @@ -881,6 +861,8 @@ module cva6
.pmpcfg_o (pmpcfg),
.pmpaddr_o (pmpaddr),
.mcountinhibit_o (mcountinhibit_csr_perf),
//RVFI
.rvfi_csr_o (rvfi_csr),
.debug_req_i,
.ipi_i,
.irq_i,
Expand Down Expand Up @@ -1374,44 +1356,45 @@ module cva6
//pragma translate_on


if (IsRVFI) begin
//RVFI INSTR

cva6_rvfi_probes #(
.CVA6Cfg (CVA6ExtendCfg),
.rvfi_probes_t(rvfi_probes_t)
) i_cva6_rvfi_combi (
cva6_rvfi_probes #(
.CVA6Cfg (CVA6ExtendCfg),
.rvfi_probes_t(rvfi_probes_t)
) i_cva6_rvfi_probes (

.flush_i (flush_ctrl_if),
.issue_instr_ack_i (issue_instr_issue_id),
.fetch_entry_valid_i(fetch_valid_if_id),
.instruction_i (fetch_entry_if_id.instruction),
.is_compressed_i (rvfi_is_compressed),
.flush_i (flush_ctrl_if),
.issue_instr_ack_i (issue_instr_issue_id),
.fetch_entry_valid_i(fetch_valid_if_id),
.instruction_i (fetch_entry_if_id.instruction),
.is_compressed_i (rvfi_is_compressed),

.issue_pointer_i (rvfi_issue_pointer),
.commit_pointer_i(rvfi_commit_pointer),
.issue_pointer_i (rvfi_issue_pointer),
.commit_pointer_i(rvfi_commit_pointer),

.flush_unissued_instr_i(flush_unissued_instr_ctrl_id),
.decoded_instr_valid_i (issue_entry_valid_id_issue),
.decoded_instr_ack_i (issue_instr_issue_id),
.flush_unissued_instr_i(flush_unissued_instr_ctrl_id),
.decoded_instr_valid_i (issue_entry_valid_id_issue),
.decoded_instr_ack_i (issue_instr_issue_id),

.rs1_forwarding_i(rs1_forwarding_id_ex),
.rs2_forwarding_i(rs2_forwarding_id_ex),
.rs1_forwarding_i(rs1_forwarding_id_ex),
.rs2_forwarding_i(rs2_forwarding_id_ex),

.commit_instr_i(commit_instr_id_commit),
.ex_commit_i (ex_commit),
.priv_lvl_i (priv_lvl),
.commit_instr_i(commit_instr_id_commit),
.ex_commit_i (ex_commit),
.priv_lvl_i (priv_lvl),

.lsu_ctrl_i (rvfi_lsu_ctrl),
.wbdata_i (wbdata_ex_id),
.commit_ack_i(commit_ack),
.mem_paddr_i (rvfi_mem_paddr),
.debug_mode_i(debug_mode),
.wdata_i (wdata_commit_id),
.lsu_ctrl_i (rvfi_lsu_ctrl),
.wbdata_i (wbdata_ex_id),
.commit_ack_i(commit_ack),
.mem_paddr_i (rvfi_mem_paddr),
.debug_mode_i(debug_mode),
.wdata_i (wdata_commit_id),

.rvfi_probes_o(rvfi_probes_o)
.csr_i(rvfi_csr),

);
.rvfi_probes_o(rvfi_probes_o)

);

end //IsRVFI

endmodule // ariane
189 changes: 147 additions & 42 deletions core/cva6_rvfi.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -14,14 +14,22 @@ module cva6_rvfi
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type rvfi_instr_t = logic,
parameter type rvfi_probes_t = logic
parameter type rvfi_csr_t = logic,
parameter type rvfi_probes_t = struct packed {
logic csr;
logic scoreboard;
logic instr;
}

) (

input logic clk_i,
input logic rst_ni,

input rvfi_probes_t rvfi_probes_i,
output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o
output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_instr_o,
output rvfi_csr_t rvfi_csr_o


);

Expand Down Expand Up @@ -146,32 +154,60 @@ module cva6_rvfi
logic [ (riscv::XLEN/8)-1:0] lsu_wmask;
logic [ TRANS_ID_BITS-1:0] lsu_addr_trans_id;

assign flush = rvfi_probes_i.flush;
assign issue_instr_ack = rvfi_probes_i.issue_instr_ack;
assign fetch_entry_valid = rvfi_probes_i.fetch_entry_valid;
assign instruction = rvfi_probes_i.instruction;
assign is_compressed = rvfi_probes_i.is_compressed;
riscv::pmpcfg_t [15:0] pmpcfg_q, pmpcfg_d;

rvfi_probes_csr_t csr;
rvfi_probes_scoreboard_t [CVA6ExtendCfg.NrCommitPorts-1:0] scoreboard;
rvfi_probes_instr_t instr;

always_comb begin
csr = '0;
scoreboard = '0;
instr = '0;

if ($size(rvfi_probes_i.instr) != 1) begin
instr = rvfi_probes_i.instr;
end

if ($size(rvfi_probes_i.scoreboard) != 1) begin
for (int i = 0; i < CVA6ExtendCfg.NrCommitPorts; i++) begin
commit_pointer[i] = rvfi_probes_i.scoreboard[i].commit_pointer;
commit_instr[i] = rvfi_probes_i.scoreboard[i].commit_instr;
wdata[i] = rvfi_probes_i.scoreboard[i].wdata;
commit_ack[i] = rvfi_probes_i.scoreboard[i].commit_ack;
end
end

if ($size(rvfi_probes_i.csr) != 1) begin
csr = rvfi_probes_i.csr;
end

end


assign issue_pointer = rvfi_probes_i.issue_pointer;
assign commit_pointer = rvfi_probes_i.commit_pointer;
assign flush = instr.flush;
assign issue_instr_ack = instr.issue_instr_ack;
assign fetch_entry_valid = instr.fetch_entry_valid;
assign instruction = instr.instruction;
assign is_compressed = instr.is_compressed;

assign flush_unissued_instr = rvfi_probes_i.flush_unissued_instr;
assign decoded_instr_valid = rvfi_probes_i.decoded_instr_valid;
assign decoded_instr_ack = rvfi_probes_i.decoded_instr_ack;
assign issue_pointer = instr.issue_pointer;

assign rs1_forwarding = rvfi_probes_i.rs1_forwarding;
assign rs2_forwarding = rvfi_probes_i.rs2_forwarding;
assign flush_unissued_instr = instr.flush_unissued_instr;
assign decoded_instr_valid = instr.decoded_instr_valid;
assign decoded_instr_ack = instr.decoded_instr_ack;

assign commit_instr = rvfi_probes_i.commit_instr;
assign ex_commit = rvfi_probes_i.ex_commit;
assign priv_lvl = rvfi_probes_i.priv_lvl;
assign rs1_forwarding = instr.rs1_forwarding;
assign rs2_forwarding = instr.rs2_forwarding;

assign lsu_ctrl = rvfi_probes_i.lsu_ctrl;
assign wbdata = rvfi_probes_i.wbdata;
assign commit_ack = rvfi_probes_i.commit_ack;
assign mem_paddr = rvfi_probes_i.mem_paddr;
assign debug_mode = rvfi_probes_i.debug_mode;
assign wdata = rvfi_probes_i.wdata;
assign ex_commit = instr.ex_commit;
assign priv_lvl = instr.priv_lvl;

assign lsu_ctrl = instr.lsu_ctrl;
assign wbdata = instr.wbdata[CVA6ExtendCfg.NrWbPorts-1:0]; //hardcoded size in probes struct

assign mem_paddr = instr.mem_paddr;
assign debug_mode = instr.debug_mode;

assign lsu_addr = lsu_ctrl.vaddr;
assign lsu_rmask = lsu_ctrl.fu == LOAD ? lsu_ctrl.be : '0;
Expand Down Expand Up @@ -263,32 +299,101 @@ module cva6_rvfi
for (int i = 0; i < CVA6ExtendCfg.NrCommitPorts; i++) begin
logic exception;
exception = commit_instr[i].valid && ex_commit.valid;
rvfi_o[i].valid = (commit_ack[i] && !ex_commit.valid) ||
rvfi_instr_o[i].valid = (commit_ack[i] && !ex_commit.valid) ||
(exception && (ex_commit.cause == riscv::ENV_CALL_MMODE ||
ex_commit.cause == riscv::ENV_CALL_SMODE ||
ex_commit.cause == riscv::ENV_CALL_UMODE));
rvfi_o[i].insn = mem_q[commit_pointer[i]].instr;
rvfi_instr_o[i].insn = mem_q[commit_pointer[i]].instr;
// when trap, the instruction is not executed
rvfi_o[i].trap = exception;
rvfi_o[i].cause = ex_commit.cause;
rvfi_o[i].mode = (CVA6ExtendCfg.DebugEn && debug_mode) ? 2'b10 : priv_lvl;
rvfi_o[i].ixl = riscv::XLEN == 64 ? 2 : 1;
rvfi_o[i].rs1_addr = commit_instr[i].rs1[4:0];
rvfi_o[i].rs2_addr = commit_instr[i].rs2[4:0];
rvfi_o[i].rd_addr = commit_instr[i].rd[4:0];
rvfi_o[i].rd_wdata = (CVA6ExtendCfg.FpPresent && is_rd_fpr(commit_instr[i].op)) ?
rvfi_instr_o[i].trap = exception;
rvfi_instr_o[i].cause = ex_commit.cause;
rvfi_instr_o[i].mode = (CVA6ExtendCfg.DebugEn && debug_mode) ? 2'b10 : priv_lvl;
rvfi_instr_o[i].ixl = riscv::XLEN == 64 ? 2 : 1;
rvfi_instr_o[i].rs1_addr = commit_instr[i].rs1[4:0];
rvfi_instr_o[i].rs2_addr = commit_instr[i].rs2[4:0];
rvfi_instr_o[i].rd_addr = commit_instr[i].rd[4:0];
rvfi_instr_o[i].rd_wdata = (CVA6ExtendCfg.FpPresent && is_rd_fpr(commit_instr[i].op)) ?
commit_instr[i].result : wdata[i];
rvfi_o[i].pc_rdata = commit_instr[i].pc;
rvfi_o[i].mem_addr = mem_q[commit_pointer[i]].lsu_addr;
rvfi_instr_o[i].pc_rdata = commit_instr[i].pc;
rvfi_instr_o[i].mem_addr = mem_q[commit_pointer[i]].lsu_addr;
// So far, only write paddr is reported. TODO: read paddr
rvfi_o[i].mem_paddr = mem_paddr;
rvfi_o[i].mem_wmask = mem_q[commit_pointer[i]].lsu_wmask;
rvfi_o[i].mem_wdata = mem_q[commit_pointer[i]].lsu_wdata;
rvfi_o[i].mem_rmask = mem_q[commit_pointer[i]].lsu_rmask;
rvfi_o[i].mem_rdata = commit_instr[i].result;
rvfi_o[i].rs1_rdata = mem_q[commit_pointer[i]].rs1_rdata;
rvfi_o[i].rs2_rdata = mem_q[commit_pointer[i]].rs2_rdata;
rvfi_instr_o[i].mem_paddr = mem_paddr;
rvfi_instr_o[i].mem_wmask = mem_q[commit_pointer[i]].lsu_wmask;
rvfi_instr_o[i].mem_wdata = mem_q[commit_pointer[i]].lsu_wdata;
rvfi_instr_o[i].mem_rmask = mem_q[commit_pointer[i]].lsu_rmask;
rvfi_instr_o[i].mem_rdata = commit_instr[i].result;
rvfi_instr_o[i].rs1_rdata = mem_q[commit_pointer[i]].rs1_rdata;
rvfi_instr_o[i].rs2_rdata = mem_q[commit_pointer[i]].rs2_rdata;
end
end


//----------------------------------------------------------------------------------------------------------
// CSR
//----------------------------------------------------------------------------------------------------------

always_comb begin

rvfi_csr_o = csr;

if (riscv::XLEN == 32) begin
pmpcfg_q[3:0] = csr.pmpcfg0.rdata;
pmpcfg_q[7:4] = csr.pmpcfg1.rdata;
pmpcfg_q[11:8] = csr.pmpcfg2.rdata;
pmpcfg_q[15:12] = csr.pmpcfg3.rdata;
pmpcfg_d[3:0] = csr.pmpcfg0.rdata;
pmpcfg_d[7:4] = csr.pmpcfg1.rdata;
pmpcfg_d[11:8] = csr.pmpcfg2.rdata;
pmpcfg_d[15:12] = csr.pmpcfg3.rdata;
pmpcfg_q[3:0] = csr.pmpcfg0.wdata;
pmpcfg_q[7:4] = csr.pmpcfg1.wdata;
pmpcfg_q[11:8] = csr.pmpcfg2.wdata;
pmpcfg_q[15:12] = csr.pmpcfg3.wdata;
pmpcfg_q[3:0] = csr.pmpcfg0.wdata;
pmpcfg_q[7:4] = csr.pmpcfg1.wdata;
pmpcfg_q[11:8] = csr.pmpcfg2.wdata;
pmpcfg_q[15:12] = csr.pmpcfg3.wdata;
end else begin
pmpcfg_q[7:0] = csr.pmpcfg0.rdata;
pmpcfg_q[15:8] = csr.pmpcfg0.rdata;
pmpcfg_d[7:0] = csr.pmpcfg0.wdata;
pmpcfg_d[15:8] = csr.pmpcfg0.wdata;
end

rvfi_csr_o.pmpaddr0.rdata[0] = pmpcfg_q[0].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr0.rdata[0] : 1'b0;
rvfi_csr_o.pmpaddr1.rdata[0] = pmpcfg_q[1].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr1.rdata[0] : 1'b0;
rvfi_csr_o.pmpaddr2.rdata[0] = pmpcfg_q[2].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr2.rdata[0] : 1'b0;
rvfi_csr_o.pmpaddr3.rdata[0] = pmpcfg_q[3].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr3.rdata[0] : 1'b0;
rvfi_csr_o.pmpaddr4.rdata[0] = pmpcfg_q[4].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr4.rdata[0] : 1'b0;
rvfi_csr_o.pmpaddr5.rdata[0] = pmpcfg_q[5].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr5.rdata[0] : 1'b0;
rvfi_csr_o.pmpaddr6.rdata[0] = pmpcfg_q[6].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr6.rdata[0] : 1'b0;
rvfi_csr_o.pmpaddr7.rdata[0] = pmpcfg_q[7].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr7.rdata[0] : 1'b0;
rvfi_csr_o.pmpaddr8.rdata[0] = pmpcfg_q[8].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr8.rdata[0] : 1'b0;
rvfi_csr_o.pmpaddr9.rdata[0] = pmpcfg_q[9].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr9.rdata[0] : 1'b0;
rvfi_csr_o.pmpaddr10.rdata[0] = pmpcfg_q[10].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr10.rdata[0] : 1'b0;
rvfi_csr_o.pmpaddr11.rdata[0] = pmpcfg_q[11].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr11.rdata[0] : 1'b0;
rvfi_csr_o.pmpaddr12.rdata[0] = pmpcfg_q[12].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr12.rdata[0] : 1'b0;
rvfi_csr_o.pmpaddr13.rdata[0] = pmpcfg_q[13].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr13.rdata[0] : 1'b0;
rvfi_csr_o.pmpaddr14.rdata[0] = pmpcfg_q[14].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr14.rdata[0] : 1'b0;
rvfi_csr_o.pmpaddr15.rdata[0] = pmpcfg_q[15].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr15.rdata[0] : 1'b0;

rvfi_csr_o.pmpaddr0.wdata[0] = pmpcfg_q[0].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr0.wdata[0] : 1'b0;
rvfi_csr_o.pmpaddr1.wdata[0] = pmpcfg_q[1].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr1.wdata[0] : 1'b0;
rvfi_csr_o.pmpaddr2.wdata[0] = pmpcfg_q[2].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr2.wdata[0] : 1'b0;
rvfi_csr_o.pmpaddr3.wdata[0] = pmpcfg_q[3].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr3.wdata[0] : 1'b0;
rvfi_csr_o.pmpaddr4.wdata[0] = pmpcfg_q[4].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr4.wdata[0] : 1'b0;
rvfi_csr_o.pmpaddr5.wdata[0] = pmpcfg_q[5].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr5.wdata[0] : 1'b0;
rvfi_csr_o.pmpaddr6.wdata[0] = pmpcfg_q[6].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr6.wdata[0] : 1'b0;
rvfi_csr_o.pmpaddr7.wdata[0] = pmpcfg_q[7].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr7.wdata[0] : 1'b0;
rvfi_csr_o.pmpaddr8.wdata[0] = pmpcfg_q[8].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr8.wdata[0] : 1'b0;
rvfi_csr_o.pmpaddr9.wdata[0] = pmpcfg_q[9].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr9.wdata[0] : 1'b0;
rvfi_csr_o.pmpaddr10.wdata[0] = pmpcfg_q[10].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr10.wdata[0] : 1'b0;
rvfi_csr_o.pmpaddr11.wdata[0] = pmpcfg_q[11].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr11.wdata[0] : 1'b0;
rvfi_csr_o.pmpaddr12.wdata[0] = pmpcfg_q[12].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr12.wdata[0] : 1'b0;
rvfi_csr_o.pmpaddr13.wdata[0] = pmpcfg_q[13].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr13.wdata[0] : 1'b0;
rvfi_csr_o.pmpaddr14.wdata[0] = pmpcfg_q[14].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr14.wdata[0] : 1'b0;
rvfi_csr_o.pmpaddr15.wdata[0] = pmpcfg_q[15].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr15.wdata[0] : 1'b0;

end


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