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csr: Implement menvcfg
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Only the `fiom` bit needs to be implemented. Since we anyway treat all
fences and atomics as fully sequential the value is currently not needed
anywhere.
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@zarubaf
zarubaf committed Nov 23, 2023
1 parent 73cd1c5 commit 6754b05
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Showing 2 changed files with 32 additions and 17 deletions.
13 changes: 13 additions & 0 deletions core/csr_regfile.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -134,6 +134,7 @@ module csr_regfile
riscv::xlen_t mepc_q, mepc_d;
riscv::xlen_t mcause_q, mcause_d;
riscv::xlen_t mtval_q, mtval_d;
logic fiom_d, fiom_q;

riscv::xlen_t stvec_q, stvec_d;
riscv::xlen_t scounteren_q, scounteren_d;
Expand Down Expand Up @@ -303,6 +304,11 @@ module csr_regfile
riscv::CSR_MCAUSE: csr_rdata = mcause_q;
riscv::CSR_MTVAL: csr_rdata = mtval_q;
riscv::CSR_MIP: csr_rdata = mip_q;
riscv::CSR_MENVCFG: csr_rdata = '0 | fiom_q;
riscv::CSR_MENVCFGH: begin
if (riscv::XLEN == 32) csr_rdata = '0;
else read_access_exception = 1'b1;
end
riscv::CSR_MVENDORID: csr_rdata = OPENHWGROUP_MVENDORID;
riscv::CSR_MARCHID: csr_rdata = ARIANE_MARCHID;
riscv::CSR_MIMPID: csr_rdata = '0; // not implemented
Expand Down Expand Up @@ -606,6 +612,7 @@ module csr_regfile
mcounteren_d = mcounteren_q;
mscratch_d = mscratch_q;
mtval_d = mtval_q;
fiom_d = fiom_q;
dcache_d = dcache_q;
icache_d = icache_q;
acc_cons_d = acc_cons_q;
Expand Down Expand Up @@ -843,6 +850,10 @@ module csr_regfile
mask = riscv::MIP_SSIP | riscv::MIP_STIP | riscv::MIP_SEIP;
mip_d = (mip_q & ~mask) | (csr_wdata & mask);
end
riscv::CSR_MENVCFG: fiom_d <= csr_wdata[0];
riscv::CSR_MENVCFGH: begin
if (riscv::XLEN != 32) update_access_exception = 1'b1;
end
riscv::CSR_MCOUNTINHIBIT:
mcountinhibit_d = {csr_wdata[MHPMCounterNum+2:2], 1'b0, csr_wdata[0]};
// performance counters
Expand Down Expand Up @@ -1516,6 +1527,7 @@ module csr_regfile
mcounteren_q <= {riscv::XLEN{1'b0}};
mscratch_q <= {riscv::XLEN{1'b0}};
mtval_q <= {riscv::XLEN{1'b0}};
fiom_q <= '0;
dcache_q <= {{riscv::XLEN - 1{1'b0}}, 1'b1};
icache_q <= {{riscv::XLEN - 1{1'b0}}, 1'b1};
mcountinhibit_q <= '0;
Expand Down Expand Up @@ -1565,6 +1577,7 @@ module csr_regfile
mcounteren_q <= mcounteren_d;
mscratch_q <= mscratch_d;
mtval_q <= mtval_d;
fiom_q <= fiom_d;
dcache_q <= dcache_d;
icache_q <= icache_d;
mcountinhibit_q <= mcountinhibit_d;
Expand Down
36 changes: 19 additions & 17 deletions core/include/riscv_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -433,6 +433,8 @@ package riscv;
CSR_MCAUSE = 12'h342,
CSR_MTVAL = 12'h343,
CSR_MIP = 12'h344,
CSR_MENVCFG = 12'h30A,
CSR_MENVCFGH = 12'h31A,
CSR_PMPCFG0 = 12'h3A0,
CSR_PMPCFG1 = 12'h3A1,
CSR_PMPCFG2 = 12'h3A2,
Expand Down Expand Up @@ -491,7 +493,7 @@ package riscv;
CSR_MHPM_COUNTER_28 = 12'hB1C, // reserved
CSR_MHPM_COUNTER_29 = 12'hB1D, // reserved
CSR_MHPM_COUNTER_30 = 12'hB1E, // reserved
CSR_MHPM_COUNTER_31 = 12'hB1F, // reserved
CSR_MHPM_COUNTER_31 = 12'hB1F, // reserved
CSR_MHPM_COUNTER_3H = 12'hB83,
CSR_MHPM_COUNTER_4H = 12'hB84,
CSR_MHPM_COUNTER_5H = 12'hB85,
Expand Down Expand Up @@ -551,14 +553,14 @@ package riscv;
CSR_HPM_COUNTER_6 = 12'hC06,
CSR_HPM_COUNTER_7 = 12'hC07,
CSR_HPM_COUNTER_8 = 12'hC08,
CSR_HPM_COUNTER_9 = 12'hC09, // reserved
CSR_HPM_COUNTER_10 = 12'hC0A, // reserved
CSR_HPM_COUNTER_11 = 12'hC0B, // reserved
CSR_HPM_COUNTER_12 = 12'hC0C, // reserved
CSR_HPM_COUNTER_13 = 12'hC0D, // reserved
CSR_HPM_COUNTER_14 = 12'hC0E, // reserved
CSR_HPM_COUNTER_15 = 12'hC0F, // reserved
CSR_HPM_COUNTER_16 = 12'hC10, // reserved
CSR_HPM_COUNTER_9 = 12'hC09, // reserved
CSR_HPM_COUNTER_10 = 12'hC0A, // reserved
CSR_HPM_COUNTER_11 = 12'hC0B, // reserved
CSR_HPM_COUNTER_12 = 12'hC0C, // reserved
CSR_HPM_COUNTER_13 = 12'hC0D, // reserved
CSR_HPM_COUNTER_14 = 12'hC0E, // reserved
CSR_HPM_COUNTER_15 = 12'hC0F, // reserved
CSR_HPM_COUNTER_16 = 12'hC10, // reserved
CSR_HPM_COUNTER_17 = 12'hC11, // reserved
CSR_HPM_COUNTER_18 = 12'hC12, // reserved
CSR_HPM_COUNTER_19 = 12'hC13, // reserved
Expand All @@ -580,14 +582,14 @@ package riscv;
CSR_HPM_COUNTER_6H = 12'hC86,
CSR_HPM_COUNTER_7H = 12'hC87,
CSR_HPM_COUNTER_8H = 12'hC88,
CSR_HPM_COUNTER_9H = 12'hC89, // reserved
CSR_HPM_COUNTER_10H = 12'hC8A, // reserved
CSR_HPM_COUNTER_11H = 12'hC8B, // reserved
CSR_HPM_COUNTER_12H = 12'hC8C, // reserved
CSR_HPM_COUNTER_13H = 12'hC8D, // reserved
CSR_HPM_COUNTER_14H = 12'hC8E, // reserved
CSR_HPM_COUNTER_15H = 12'hC8F, // reserved
CSR_HPM_COUNTER_16H = 12'hC90, // reserved
CSR_HPM_COUNTER_9H = 12'hC89, // reserved
CSR_HPM_COUNTER_10H = 12'hC8A, // reserved
CSR_HPM_COUNTER_11H = 12'hC8B, // reserved
CSR_HPM_COUNTER_12H = 12'hC8C, // reserved
CSR_HPM_COUNTER_13H = 12'hC8D, // reserved
CSR_HPM_COUNTER_14H = 12'hC8E, // reserved
CSR_HPM_COUNTER_15H = 12'hC8F, // reserved
CSR_HPM_COUNTER_16H = 12'hC90, // reserved
CSR_HPM_COUNTER_17H = 12'hC91, // reserved
CSR_HPM_COUNTER_18H = 12'hC92, // reserved
CSR_HPM_COUNTER_19H = 12'hC93, // reserved
Expand Down

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