Update csr_regfile.sv

core/csr_regfile.sv

@@ -1288,28 +1288,32 @@ module csr_regfile
       CSR_SET:   csr_wdata = csr_wdata_i | csr_rdata;
       CSR_CLEAR: csr_wdata = (~csr_wdata_i) & csr_rdata;
       CSR_READ:  csr_we = 1'b0;
+      SRET: begin
+        if (CVA6Cfg.RVS) begin
+          // the return should not have any write or read side-effects
+          csr_we   = 1'b0;
+          csr_read = 1'b0;
+          sret     = 1'b1;  // signal a return from supervisor mode
+        end
+      end
       MRET: begin
         // the return should not have any write or read side-effects
         csr_we   = 1'b0;
         csr_read = 1'b0;
         mret     = 1'b1;  // signal a return from machine mode
       end
-      default: begin
-        if (CVA6Cfg.RVS && csr_op_i == SRET) begin
-          // the return should not have any write or read side-effects
-          csr_we   = 1'b0;
-          csr_read = 1'b0;
-          sret     = 1'b1;  // signal a return from supervisor mode
-        end else if (CVA6Cfg.DebugEn && csr_op_i == DRET) begin
+      DRET: begin
+        if (CVA6Cfg.DebugEn) begin
           // the return should not have any write or read side-effects
           csr_we   = 1'b0;
           csr_read = 1'b0;
           dret     = 1'b1;  // signal a return from debug mode
-        end else begin
-          csr_we   = 1'b0;
-          csr_read = 1'b0;
         end
       end
+      default: begin
+        csr_we   = 1'b0;
+        csr_read = 1'b0;
+      end
     endcase
     // if we are violating our privilges do not update the architectural state
     if (privilege_violation) begin