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lint fixes
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@farhan-108
farhan-108 committed Dec 11, 2024
1 parent fba9b6a commit 645d24f
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Showing 6 changed files with 33 additions and 32 deletions.
4 changes: 2 additions & 2 deletions core/compressed_decoder.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ module compressed_decoder #(
is_compressed_o = 1'b1;
instr_o = instr_i;
is_macro_instr_o = 0;
is_zcmt_instr_o = 0;
is_zcmt_instr_o = 1'b0;

// I: | imm[11:0] | rs1 | funct3 | rd | opcode |
// S: | imm[11:5] | rs2 | rs1 | funct3 | imm[4:0] | opcode |
Expand Down Expand Up @@ -875,7 +875,7 @@ module compressed_decoder #(
is_macro_instr_o = 1;
instr_o = instr_i;
end else if (instr_i[12:10] == 3'b000) begin //jt/jalt instruction
is_zcmt_instr_o = 1;
is_zcmt_instr_o = 1'b1;
end else begin
illegal_instr_o = 1'b1;
end
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2 changes: 2 additions & 0 deletions core/cva6.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -1297,8 +1297,10 @@ module cva6
// Cache port 0 is being ultilized in implicit read access in ZCMT extension.
if (CVA6Cfg.RVZCMT & ~(CVA6Cfg.MmuPresent)) begin
assign dcache_req_ports_cache_id = dcache_req_from_cache[0];
assign dcache_req_ports_cache_ex[0] = '0;
end else begin
assign dcache_req_ports_cache_ex[0] = dcache_req_from_cache[0];
assign dcache_req_ports_cache_id = '0;
end
assign dcache_req_ports_cache_ex[1] = dcache_req_from_cache[1];
assign dcache_req_ports_cache_acc[0] = dcache_req_from_cache[2];
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4 changes: 2 additions & 2 deletions core/ex_stage.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -321,8 +321,8 @@ module ex_stage
.v_i,
.debug_mode_i,
.fu_data_i (one_cycle_data),
.pc_i,
.is_zcmt_i,
.pc_i (pc_i),
.is_zcmt_i (is_zcmt_i),
.is_compressed_instr_i,
.branch_valid_i (|branch_valid_i),
.branch_comp_res_i (alu_branch_res),
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37 changes: 18 additions & 19 deletions core/id_stage.sv
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Expand Up @@ -111,24 +111,23 @@ module id_stage #(

logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal;
logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_cmp;
logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_cvxif, is_illegal_cvxif_zcmp, is_illegal_cvxif_zcmt;
logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_cvxif;
logic is_illegal_cvxif_zcmp, is_illegal_cvxif_zcmt;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] compressed_instr;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0]
instruction_cvxif, instruction_cvxif_zcmp, instruction_cvxif_zcmt;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_cvxif;
logic [31:0] instruction_cvxif_zcmp, instruction_cvxif_zcmt;
logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed;
logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_cmp;
logic [CVA6Cfg.NrIssuePorts-1:0]
is_compressed_cvxif, is_compressed_cvxif_zcmp, is_compressed_cvxif_zcmt;
logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_cvxif;
logic is_compressed_cvxif_zcmp, is_compressed_cvxif_zcmt;

logic [CVA6Cfg.NrIssuePorts-1:0] is_macro_instr_i;
logic stall_instr_fetch;
logic stall_macro_deco, stall_macro_deco_zcmp, stall_macro_deco_zcmt;
logic is_last_macro_instr_o;
logic is_double_rd_macro_instr_o;
logic [CVA6Cfg.NrIssuePorts-1:0] is_zcmt_instr_i;
branchpredict_sbe_t branch_predict;
logic is_zcmt;
logic is_last_macro_instr_o;
logic is_double_rd_macro_instr_o;
logic [CVA6Cfg.NrIssuePorts-1:0] is_zcmt_instr_i;

if (CVA6Cfg.RVC) begin
// ---------------------------------------------------------
Expand All @@ -155,12 +154,12 @@ module id_stage #(
.is_macro_instr_i (is_macro_instr_i[0]),
.clk_i (clk_i),
.rst_ni (rst_ni),
.instr_o (instruction_cvxif_zcmp[0]),
.instr_o (instruction_cvxif_zcmp),
.illegal_instr_i (is_illegal[0]),
.is_compressed_i (is_compressed[0]),
.issue_ack_i (issue_instr_ack_i[0]),
.illegal_instr_o (is_illegal_cvxif_zcmp[0]),
.is_compressed_o (is_compressed_cvxif_zcmp[0]),
.illegal_instr_o (is_illegal_cvxif_zcmp),
.is_compressed_o (is_compressed_cvxif_zcmp),
.fetch_stall_o (stall_macro_deco_zcmp),
.is_last_macro_instr_o (is_last_macro_instr_o),
.is_double_rd_macro_instr_o(is_double_rd_macro_instr_o)
Expand All @@ -177,20 +176,20 @@ module id_stage #(
.is_zcmt_instr_i(is_zcmt_instr_i[0]),
.clk_i (clk_i),
.rst_ni (rst_ni),
.instr_o (instruction_cvxif_zcmt[0]),
.instr_o (instruction_cvxif_zcmt),
.illegal_instr_i(is_illegal[0]),
.is_compressed_i(is_compressed[0]),
.illegal_instr_o(is_illegal_cvxif_zcmt[0]),
.is_compressed_o(is_compressed_cvxif_zcmt[0]),
.illegal_instr_o(is_illegal_cvxif_zcmt),
.is_compressed_o(is_compressed_cvxif_zcmt),
.fetch_stall_o (stall_macro_deco_zcmt),
.jvt_i (jvt_i),
.req_port_i (dcache_req_ports_i),
.req_port_o (dcache_req_ports_o)
);

assign instruction_cvxif[0] = is_zcmt_instr_i[0] ? instruction_cvxif_zcmt[0] : instruction_cvxif_zcmp[0];
assign is_illegal_cvxif[0] = is_zcmt_instr_i[0] ? is_illegal_cvxif_zcmt[0] : is_illegal_cvxif_zcmp[0];
assign is_compressed_cvxif[0] = is_zcmt_instr_i[0] ? is_compressed_cvxif_zcmt[0] : is_compressed_cvxif_zcmp[0];
assign instruction_cvxif[0] = is_zcmt_instr_i[0] ? instruction_cvxif_zcmt : instruction_cvxif_zcmp;
assign is_illegal_cvxif[0] = is_zcmt_instr_i[0] ? is_illegal_cvxif_zcmt : is_illegal_cvxif_zcmp;
assign is_compressed_cvxif[0] = is_zcmt_instr_i[0] ? is_compressed_cvxif_zcmt : is_compressed_cvxif_zcmp;
assign stall_macro_deco = is_zcmt_instr_i[0] ? stall_macro_deco_zcmt : stall_macro_deco_zcmp;
if (CVA6Cfg.SuperscalarEn) begin
assign instruction_cvxif[CVA6Cfg.NrIssuePorts-1] = '0;
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2 changes: 1 addition & 1 deletion core/issue_stage.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -264,7 +264,7 @@ module issue_stage
.fu_data_o (fu_data_o),
.rs1_forwarding_o (rs1_forwarding_xlen),
.rs2_forwarding_o (rs2_forwarding_xlen),
.pc_o,
.pc_o (pc_o),
.is_zcmt_o (is_zcmt_o),
.is_compressed_instr_o,
.flu_ready_i (flu_ready_i),
Expand Down
16 changes: 8 additions & 8 deletions core/zcmt_decoder.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -35,10 +35,9 @@ module zcmt_decoder #(
}
state_d, state_q;
// Temporary registers
logic [7:0] index; //index of instruction
//Physical address: jvt + (index <<2)
logic [CVA6Cfg.XLEN+1:0] table_address; //Virtual address: {00,Physical address}
logic [20:0] jump_addr; //jump address immidiate
logic [31:0] jump_addr; //jump address immidiate

always_comb begin
state_d = state_q;
Expand All @@ -47,21 +46,22 @@ module zcmt_decoder #(
fetch_stall_o = is_zcmt_instr_i ? 1'b1 : 0;

//cache request port
req_port_o.data_wdata = 1'b0;
req_port_o.data_wdata = '0;
req_port_o.data_wuser = '0;
req_port_o.data_req = 1'b0;
req_port_o.data_we = 1'b0;
req_port_o.data_be = 1'b0;
req_port_o.data_be = '0;
req_port_o.data_size = 2'b10;
req_port_o.data_id = 1;
req_port_o.kill_req = 0;
req_port_o.tag_valid = 1;
req_port_o.data_id = 1'b1;
req_port_o.kill_req = 1'b0;
req_port_o.tag_valid = 1'b1;

unique case (state_q)
IDLE: begin
if (is_zcmt_instr_i) begin
if (CVA6Cfg.XLEN == 32) begin //It is only target for 32 bit targets in cva6 with No MMU
table_address = {2'b00, ({jvt_i.base, jvt_i.mode} + (instr_i[9:2] << 2))};
// table_address = {2'b00, ({jvt_i.base, instr_i[7:2], 2'b00})};
table_address = {2'b00, ({jvt_i.base, jvt_i.mode} + {24'h0, instr_i[7:2], 2'b00})};
req_port_o.address_index = table_address[9:0];
req_port_o.address_tag = table_address[33:10];
state_d = TABLE_JUMP;
Expand Down

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