Move timing statement outside of always_comb block (#2552)

Fix following requirement:

The assertion included in the always_comb block apparently violates the requirements in [section 9.2.2.2.2 of the SystemVerilog standard](https://ieeexplore.ieee.org/document/10458102):

Statements in an always_comb shall not include those that block, have blocking timing or event
controls, or fork-join statements.

core/cache_subsystem/tag_cmp.sv

@@ -81,6 +81,8 @@ module tag_cmp #(
       if (req_i[i]) break;
     end
 
+  end
+
 `ifndef SYNTHESIS
 `ifndef VERILATOR
     // assert that cache only hits on one way
@@ -92,7 +94,6 @@ module tag_cmp #(
     end
 `endif
 `endif
-  end
 
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (~rst_ni) begin