Merge branch 'master' into uga_fpetrot_02082024

.gitlab-ci.yml

@@ -131,9 +131,9 @@ build_tools:
     - echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC
 
 .simu_after_script: &simu_after_script
-  - for i in $(find verif/sim/out*/[vq]*_sim -type f \( -name "*.csv" -o -name "*.iss" \)) ; do head -10000 $i > artifacts/logs/$(basename $i).head ; done
+  - for i in $(find verif/sim/out*/[vq]*_sim -type f \( -name "*.csv" -o -name "*.iss" -o -name "*.yaml" \)) ; do head -10000 $i > artifacts/logs/$(basename $i).head ; done
   - head -10000 verif/sim/logfile.log > artifacts/logs/logfile.log.head
-  - python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log
+  - if [ -n "$SPIKE_TANDEM" ]; then python3 .gitlab-ci/scripts/report_tandem.py verif/sim/out*/"$DV_SIMULATORS"_sim; else python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log; fi
 
 smoke:
   extends:
@@ -149,12 +149,13 @@ smoke:
     matrix:
       - DV_SIMULATORS:
         - "veri-testharness,spike"
-        - "vcs-testharness,spike"
+        - "vcs-testharness"
         - "questa-testharness,spike"
-        - "vcs-uvm,spike"
+        - "vcs-uvm"
   script:
     - source $QUESTA_BASHRC
     - bash verif/regress/smoke-tests.sh
+    - if [[ $DV_SIMULATORS == *"spike"* ]]; then unset SPIKE_TANDEM; fi # dirty hack to do trace comparison between tandem execution and spike standalone
     - !reference [.simu_after_script]
 
 gen_smoke:
@@ -165,9 +166,9 @@ gen_smoke:
     DASHBOARD_JOB_DESCRIPTION: "Short generated tests to challenge the CVA6-DV on STEP1 configuration"
     DASHBOARD_SORT_INDEX: 0
     DASHBOARD_JOB_CATEGORY: "Basic"
-    DV_SIMULATORS: "vcs-uvm,spike"
-    SPIKE_TANDEM: 1
+    DV_SIMULATORS: "vcs-uvm"
     COLLECT_SIMU_LOGS: 1
+    SPIKE_TANDEM: 1
   script:
     - bash verif/regress/smoke-gen_tests.sh
     - !reference [.simu_after_script]
@@ -230,8 +231,27 @@ spyglass:
     - make -C spyglass design_read
     - make -C spyglass lint_check
     - mv spyglass/sg_run_results/cva6_sg_reports/cva6_lint_lint_rtl artifacts/lint_reports
+    - cp spyglass/reference_summary.rpt artifacts/lint_reports
     - python3 .gitlab-ci/scripts/report_spyglass_lint.py spyglass/reference_summary.rpt artifacts/lint_reports/cva6_lint_lint_rtl/summary.rpt
 
+cvxif-regression:
+  extends:
+    - .synthesis_test
+  variables:
+    DASHBOARD_JOB_TITLE: "CVXIF non-regression test $DV_SIMULATORS"
+    DASHBOARD_JOB_DESCRIPTION: "Short tests to challenge most CoreV-X-Interface in testharness"
+    DASHBOARD_SORT_INDEX: 5
+    DASHBOARD_JOB_CATEGORY: "Basic"
+    COLLECT_SIMU_LOGS: 1
+  parallel:
+    matrix:
+      - DV_SIMULATORS:
+        - "veri-testharness,spike"
+        - "vcs-testharness,spike"
+  script:
+    - bash verif/regress/cvxif_verif_regression.sh
+    - !reference [.simu_after_script]
+
 asic-synthesis:
   extends:
     - .synthesis_test
@@ -307,7 +327,8 @@ riscv_arch_test:
     DASHBOARD_JOB_DESCRIPTION: "Compliance regression suite"
     DASHBOARD_SORT_INDEX: 0
     DASHBOARD_JOB_CATEGORY: "Test suites"
-    DV_SIMULATORS: "veri-testharness,spike"
+    DV_SIMULATORS: "vcs-testharness"
+    SPIKE_TANDEM: 1
   script: source verif/regress/dv-riscv-arch-test.sh
   after_script: *simu_after_script
 
@@ -319,7 +340,8 @@ compliance:
     DASHBOARD_JOB_DESCRIPTION: "Compliance regression suite"
     DASHBOARD_SORT_INDEX: 2
     DASHBOARD_JOB_CATEGORY: "Test suites"
-    DV_SIMULATORS: "veri-testharness,spike"
+    DV_SIMULATORS: "vcs-testharness"
+    SPIKE_TANDEM: 1
   script: source verif/regress/dv-riscv-compliance.sh
   after_script: *simu_after_script
 
@@ -331,9 +353,10 @@ riscv-tests-v:
     DASHBOARD_JOB_DESCRIPTION: "Riscv-test regression suite (virtual)"
     DASHBOARD_SORT_INDEX: 3
     DASHBOARD_JOB_CATEGORY: "Test suites"
-    DV_SIMULATORS: "veri-testharness,spike"
+    DV_SIMULATORS: "vcs-testharness"
     DV_TARGET: cv64a6_imafdc_sv39
     DV_TESTLISTS: "../tests/testlist_riscv-tests-$DV_TARGET-v.yaml"
+    SPIKE_TANDEM: 1
   script: source verif/regress/dv-riscv-tests.sh
   after_script: *simu_after_script
 
@@ -345,8 +368,9 @@ riscv-tests-p:
     DASHBOARD_JOB_DESCRIPTION: "Riscv-test regression suite (physical)"
     DASHBOARD_SORT_INDEX: 4
     DASHBOARD_JOB_CATEGORY: "Test suites"
-    DV_SIMULATORS: "veri-testharness,spike"
+    DV_SIMULATORS: "vcs-testharness"
     DV_TESTLISTS: "../tests/testlist_riscv-tests-$DV_TARGET-p.yaml"
+    SPIKE_TANDEM: 1
   script: source verif/regress/dv-riscv-tests.sh
   after_script: *simu_after_script
 
@@ -368,8 +392,9 @@ mmu_sv32_tests:
     DASHBOARD_JOB_DESCRIPTION: "MMU SV32 regression suite"
     DASHBOARD_SORT_INDEX: 0
     DASHBOARD_JOB_CATEGORY: "Test suites"
-    DV_SIMULATORS: "veri-testharness,spike"
+    DV_SIMULATORS: "vcs-testharness"
     DV_TARGET: cv32a6_imac_sv32
+    SPIKE_TANDEM: 1
   script: source verif/regress/dv-riscv-mmu-sv32-test.sh
   after_script: *simu_after_script
 

.gitlab-ci/expected_synth.yml

@@ -1,2 +1,2 @@
 cv32a65x:
-  gates: 171002
+  gates: 171460

.gitlab-ci/scripts/report_spyglass_lint.py

@@ -11,7 +11,6 @@
 
 import re
 import sys
-import subprocess
 import report_builder as rb
 
 
@@ -69,15 +68,17 @@ def compare_summaries(baseline_info, new_info):
                 message = (
                     f"Count changed from {baseline_dict[key][0]} to {new_dict[key][0]}"
                 )
-                comparison_results.append((*key, *value, "FAIL", message))
+                if key[0] == "ERROR" and new_dict[key][0] > baseline_dict[key][0]:
+                    comparison_results.append((*key, *value, "FAIL", message))
+                else:
+                    comparison_results.append((*key, *value, "PASS", message))
 
     severity_order = {"ERROR": 1, "WARNING": 2, "INFO": 3}
     comparison_results.sort(key=lambda x: severity_order[x[0]])
-
     return comparison_results
 
 
-def report_spyglass_lint(comparison_results):
+def generate_spyglass_lint_report(comparison_results):
     metric = rb.TableStatusMetric("")
     metric.add_column("SEVERITY", "text")
     metric.add_column("RULE NAME", "text")
@@ -94,27 +95,10 @@ def report_spyglass_lint(comparison_results):
 
     report = rb.Report()
     report.add_metric(metric)
-    report.dump()
-
 
-def run_diff(ref_file, new_file):
-    result = subprocess.run(
-        [
-            "diff",
-            "-I",
-            r"#\s+Report Name\s+:\s*[^#]*#\s+Report Created by\s*:\s*[^#]*#\s+Report Created on\s*:\s*[^#]*#\s+Working Directory\s*:\s*[^#]*",
-            ref_file,
-            new_file,
-        ],
-        capture_output=True,
-        text=True,
-    )
-    if result.stdout:
-        print("Found differences between reference and new summary")
-        return False
-    else:
-        print("No differences found between reference and new summary")
-        return True
+    for value in metric.values:
+        print(" | ".join(map(str, value)))
+    return report
 
 
 if __name__ == "__main__":
@@ -124,13 +108,11 @@ def run_diff(ref_file, new_file):
     summary_ref_results = sys.argv[1]
     summary_rpt = sys.argv[2]
 
-    no_diff = run_diff(summary_ref_results, summary_rpt)
-
     baseline_info = extract_info(summary_ref_results)
     new_info = extract_info(summary_rpt)
     comparison_results = compare_summaries(baseline_info, new_info)
-    report_spyglass_lint(comparison_results)
-
-    if not no_diff:
-        print("Job failed due to differences in summaries")
+    report = generate_spyglass_lint_report(comparison_results)
+    print(report.failed)
+    report.dump()
+    if report.failed:
         sys.exit(1)

.gitlab-ci/scripts/report_tandem.py

@@ -0,0 +1,97 @@
+# Copyright 2024 Thales DIS France SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 0.51 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Valentin Thomazic ([email protected])
+
+import sys
+import report_builder
+import os
+import glob
+import yaml
+
+
+def main():
+    with_logs = os.environ.get("COLLECT_SIMU_LOGS") != None
+    metrics_table = report_builder.TableStatusMetric('')
+
+    check_provided_args()
+    add_table_legend(metrics_table, with_logs)
+    passed_tests_count, total_tests_count = fill_table(sys.argv[1], metrics_table, with_logs)
+
+    if not report(metrics_table, passed_tests_count, total_tests_count):
+        sys.exit(1)
+
+
+def check_provided_args():
+    if sys.argv[1] is None or not isinstance(sys.argv[1], str):
+        print("Usage : python report_tandem.py path/to/log/dir", file=sys.stderr)
+        sys.exit("No log directory provided !")
+
+
+def add_table_legend(metrics_table, with_logs):
+    metrics_table.add_column("TARGET", "text")
+    metrics_table.add_column("ISA", "text")
+    metrics_table.add_column("TEST", "text")
+    metrics_table.add_column("TEST LIST", "text")
+    metrics_table.add_column("SIMULATOR", "text")
+    metrics_table.add_column("MISMATCHES", "text")
+
+    if with_logs:
+        metrics_table.add_column("OUTPUT", "log")
+        metrics_table.add_column("TB LOGS", "log")
+        metrics_table.add_column("DISASSEMBLY", "log")
+
+
+def fill_table(reports_dir, metrics_table, with_logs):
+    simulation_reports = glob.iglob(reports_dir + "/*.yaml")
+    test_passed = 0
+    test_count = 0
+
+    for report in simulation_reports:
+        test_passed += add_test_row(report, metrics_table, with_logs)
+        test_count += 1
+    if test_passed != test_count:
+        metrics_table.fail()
+    return test_passed, test_count
+
+
+def add_test_row(report_file, metrics_table, with_logs):
+    with open(report_file) as f:
+        report = yaml.safe_load(f)
+    mismatches_count = str(report["mismatches_count"]) if "mismatches_count" in report else "Not found"
+
+    row = [report["target"], report["isa"], report["test"], report["testlist"], report["simulator"], mismatches_count]
+
+    if with_logs:
+        logs_path = "logs/" + os.environ.get("CI_JOB_ID") + "/artifacts/logs/"
+        output_log = logs_path + "logfile.log.head"
+        log_prefix = logs_path + report['test'] + "_" + str(report["iteration"]) + "." + report["target"] \
+            if "iteration" in report else logs_path + report['test'] + "." + report["target"]
+        tb_log = log_prefix + '.log.iss.head'
+        disassembly = log_prefix + '.log.csv.head'
+
+        row.append(output_log)
+        row.append(tb_log)
+        row.append(disassembly)
+
+    if report["exit_cause"] == "SUCCESS" and report["exit_code"] == 0:
+        metrics_table.add_pass(*row)
+        return 1
+
+    metrics_table.add_fail(*row)
+    return 0
+
+
+def report(metrics_table, passed_test_count, total_test_count):
+    report = report_builder.Report(f'{passed_test_count}/{total_test_count}')
+    report.add_metric(metrics_table)
+    report.dump()
+    return not report.failed
+
+
+if __name__ == "__main__":
+    main()

Makefile

@@ -271,12 +271,12 @@ incdir := $(CVA6_REPO_DIR)/vendor/pulp-platform/common_cells/include/ $(CVA6_REP
           $(SPIKE_INSTALL_DIR)/include/disasm/
 
 # Compile and sim flags
-compile_flag     += -incr -64 -nologo -quiet -suppress 13262 -suppress 8607 -permissive -svinputport=compat +define+$(defines) -suppress 8386 -suppress vlog-2577
+compile_flag     += -incr -64 -nologo -quiet -suppress 13262 -suppress 8607 +permissive -svinputport=compat +define+$(defines) -suppress 8386 -suppress vlog-2577
 vopt_flag += -suppress 2085 -suppress 7063 -suppress 2698 -suppress 13262
 
 uvm-flags        += +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
 questa-flags     += -t 1ns -64 $(gui-sim) $(QUESTASIM_FLAGS) \
-			+tohost_addr=$(hell ${RISCV}/bin/${CV_SW_PREFIX}nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \
+			+tohost_addr=$(shell ${RISCV}/bin/${CV_SW_PREFIX}nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \
 			+core_name=$(target) +define+QUESTA -suppress 3356 -suppress 3579
 compile_flag_vhd += -64 -nologo -quiet -2008
 
@@ -307,7 +307,7 @@ ifdef preload
 endif
 
 ifdef spike-tandem
-    questa-cmd += -gblso $(SPIKE_INSTALL_DIR)/lib/libriscv.so
+    questa-cmd += -gblso $(SPIKE_INSTALL_DIR)/lib/libyaml-cpp.so -gblso $(SPIKE_INSTALL_DIR)/lib/libriscv.so
 endif
 
 # remote bitbang is enabled
@@ -726,6 +726,8 @@ fpga_filter += $(addprefix $(root-dir), src/util/instr_trace_item.sv)
 fpga_filter += $(addprefix $(root-dir), common/local/util/instr_tracer.sv)
 fpga_filter += $(addprefix $(root-dir), vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv)
 fpga_filter += $(addprefix $(root-dir), common/local/util/tc_sram_wrapper.sv)
+fpga_filter += $(addprefix $(root-dir), corev_apu/tb/ariane_peripherals.sv)
+fpga_filter += $(addprefix $(root-dir), corev_apu/tb/ariane_testharness.sv)
 
 src/bootrom/bootrom_$(XLEN).sv:
 	$(MAKE) -C corev_apu/fpga/src/bootrom BOARD=$(BOARD) XLEN=$(XLEN) bootrom_$(XLEN).sv

README.md

@@ -1,6 +1,8 @@
 ![Build Status](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml/badge.svg?branch=master)
 
 
+[CVA6 dashboard](util/toolchain-builder/README.md#Prerequisites)
+
 # CVA6 RISC-V CPU
 
 CVA6 is a 6-stage, single-issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M, A and C extensions as specified in Volume I: User-Level ISA V 2.3 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore, it is compliant to the draft external debug spec 0.13.

config/gen_from_riscv_config/cv32a65x/spike/spike.yaml

@@ -8,24 +8,25 @@ spike_param_tree:
   generic_core_config: false
   max_steps: 200000
   max_steps_enabled: false
-  isa: rv32imczicsr_zicntr_zifencei_zcb_zba_zbb_zbc_zbs
+  isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs
   priv: M
-  cores:
-  - isa: rv32imc_zba_zbb_zbs_zbc_zicsr_zifencei
-    boot_addr: 2147483648
-    marchid: 3
-    misa_we: false
-    misa_we_enable: true
-    pmpaddr0: 0
-    pmpcfg0: 0
-    pmpregions: 64
-    usable_pmpregions: 8
-    priv: M
-    status_fs_field_we: false
-    status_fs_field_we_enable: false
-    status_vs_field_we: false
-    status_vs_field_we_enable: false
-    mstatus_write_mask: 136
-    mstatus_override_mask: 6144
-    mtval_write_mask: 0
-    unified_traps: true
+  core_configs:
+    -
+      isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs
+      boot_addr: 2147483648
+      marchid: 3
+      misa_we: false
+      misa_we_enable: true
+      pmpaddr0: 0
+      pmpcfg0: 0
+      pmpregions: 64
+      usable_pmpregions: 8
+      priv: M
+      status_fs_field_we: false
+      status_fs_field_we_enable: false
+      status_vs_field_we: false
+      status_vs_field_we_enable: false
+      mstatus_write_mask: 136
+      mstatus_override_mask: 6144
+      mtval_write_mask: 0
+      unified_traps: true

config/riscv-config/cv32a65x/generated/isa_gen.yaml

@@ -16,7 +16,7 @@
 
 hart_ids: [0]
 hart0:
-    ISA: RV32IMCZicsr_Zicntr_Zcb_Zba_Zbb_Zbc_Zbs
+    ISA: RV32IMCZicsr_Zcb_Zba_Zbb_Zbc_Zbs
     User_Spec_Version: '2.3'
     supported_xlen:
       - 32