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format: apply Verible
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@cathales
cathales committed Mar 8, 2024
1 parent cf1d838 commit 472308e
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Showing 15 changed files with 89 additions and 89 deletions.
16 changes: 8 additions & 8 deletions core/cache_subsystem/cva6_hpdcache_if_adapter.sv
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Expand Up @@ -15,10 +15,10 @@ module cva6_hpdcache_if_adapter
// Parameters
// {{{
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter bit is_load_port = 1'b1
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter bit is_load_port = 1'b1
)
// }}}

Expand All @@ -33,10 +33,10 @@ module cva6_hpdcache_if_adapter
input hpdcache_pkg::hpdcache_req_sid_t hpdcache_req_sid_i,

// Request/response ports from/to the CVA6 core
input dcache_req_i_t cva6_req_i,
output dcache_req_o_t cva6_req_o,
input ariane_pkg::amo_req_t cva6_amo_req_i,
output ariane_pkg::amo_resp_t cva6_amo_resp_o,
input dcache_req_i_t cva6_req_i,
output dcache_req_o_t cva6_req_o,
input ariane_pkg::amo_req_t cva6_amo_req_i,
output ariane_pkg::amo_resp_t cva6_amo_resp_o,

// Request port to the L1 Dcache
output logic hpdcache_req_valid_o,
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26 changes: 13 additions & 13 deletions core/cache_subsystem/cva6_hpdcache_subsystem.sv
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Expand Up @@ -68,17 +68,17 @@ module cva6_hpdcache_subsystem
output logic dcache_miss_o, // we missed on a ld/st

// AMO interface
input ariane_pkg::amo_req_t dcache_amo_req_i, // from LSU
output ariane_pkg::amo_resp_t dcache_amo_resp_o, // to LSU
input ariane_pkg::amo_req_t dcache_amo_req_i, // from LSU
output ariane_pkg::amo_resp_t dcache_amo_resp_o, // to LSU
// CMO interface
input cmo_req_t dcache_cmo_req_i, // from CMO FU
output cmo_rsp_t dcache_cmo_resp_o, // to CMO FU
input cmo_req_t dcache_cmo_req_i, // from CMO FU
output cmo_rsp_t dcache_cmo_resp_o, // to CMO FU
// Request ports
input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // from LSU
output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to LSU
input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // from LSU
output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to LSU
// Write Buffer status
output logic wbuffer_empty_o,
output logic wbuffer_not_ni_o,
output logic wbuffer_empty_o,
output logic wbuffer_not_ni_o,

// Hardware memory prefetcher configuration
input logic [NrHwPrefetchers-1:0] hwpf_base_set_i,
Expand Down Expand Up @@ -119,7 +119,7 @@ module cva6_hpdcache_subsystem
.icache_drsp_t(icache_drsp_t),
.icache_req_t(icache_req_t),
.icache_rtrn_t(icache_rtrn_t),
.RdTxId (ICACHE_RDTXID)
.RdTxId(ICACHE_RDTXID)
) i_cva6_icache (
.clk_i (clk_i),
.rst_ni (rst_ni),
Expand Down Expand Up @@ -232,10 +232,10 @@ module cva6_hpdcache_subsystem
assign dcache_req_ports[r] = dcache_req_ports_i[r];

cva6_hpdcache_if_adapter #(
.CVA6Cfg (CVA6Cfg),
.CVA6Cfg (CVA6Cfg),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.is_load_port(1'b1)
.is_load_port (1'b1)
) i_cva6_hpdcache_load_if_adapter (
.clk_i,
.rst_ni,
Expand All @@ -260,10 +260,10 @@ module cva6_hpdcache_subsystem
end

cva6_hpdcache_if_adapter #(
.CVA6Cfg (CVA6Cfg),
.CVA6Cfg (CVA6Cfg),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.is_load_port(1'b0)
.is_load_port (1'b0)
) i_cva6_hpdcache_store_if_adapter (
.clk_i,
.rst_ni,
Expand Down
12 changes: 6 additions & 6 deletions core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv
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Expand Up @@ -49,13 +49,13 @@ module cva6_hpdcache_subsystem_axi_arbiter

// Interfaces from/to I$
// {{{
input logic icache_miss_valid_i,
output logic icache_miss_ready_o,
input icache_req_t icache_miss_i,
input hpdcache_mem_id_t icache_miss_id_i,
input logic icache_miss_valid_i,
output logic icache_miss_ready_o,
input icache_req_t icache_miss_i,
input hpdcache_mem_id_t icache_miss_id_i,

output logic icache_miss_resp_valid_o,
output icache_rtrn_t icache_miss_resp_o,
output logic icache_miss_resp_valid_o,
output icache_rtrn_t icache_miss_resp_o,
// }}}

// Interfaces from/to D$
Expand Down
12 changes: 6 additions & 6 deletions core/cache_subsystem/miss_handler.sv
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Expand Up @@ -20,12 +20,12 @@ module miss_handler
import ariane_pkg::*;
import std_cache_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter int unsigned NR_PORTS = 4,
parameter type axi_req_t = logic,
parameter type axi_rsp_t = logic,
parameter type cache_line_t = logic,
parameter type cl_be_t = logic
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter int unsigned NR_PORTS = 4,
parameter type axi_req_t = logic,
parameter type axi_rsp_t = logic,
parameter type cache_line_t = logic,
parameter type cl_be_t = logic
) (
input logic clk_i,
input logic rst_ni,
Expand Down
6 changes: 3 additions & 3 deletions core/cache_subsystem/std_cache_subsystem.sv
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Expand Up @@ -76,7 +76,7 @@ module std_cache_subsystem
axi_rsp_t axi_resp_data;

cva6_icache_axi_wrapper #(
.CVA6Cfg (CVA6Cfg),
.CVA6Cfg(CVA6Cfg),
.icache_areq_t(icache_areq_t),
.icache_arsp_t(icache_arsp_t),
.icache_dreq_t(icache_dreq_t),
Expand Down Expand Up @@ -106,10 +106,10 @@ module std_cache_subsystem
// Port 2: Accelerator
// Port 3: Store Unit
std_nbdcache #(
.CVA6Cfg (CVA6Cfg),
.CVA6Cfg(CVA6Cfg),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.NumPorts (NumPorts),
.NumPorts(NumPorts),
.axi_req_t(axi_req_t),
.axi_rsp_t(axi_rsp_t)
) i_nbdcache (
Expand Down
6 changes: 3 additions & 3 deletions core/cache_subsystem/std_nbdcache.sv
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Expand Up @@ -53,7 +53,7 @@ module std_nbdcache
logic dirty; // state array
};
localparam type cl_be_t = struct packed {
logic [(ariane_pkg::DCACHE_TAG_WIDTH+7)/8-1:0] tag; // byte enable into tag array
logic [(ariane_pkg::DCACHE_TAG_WIDTH+7)/8-1:0] tag; // byte enable into tag array
logic [(ariane_pkg::DCACHE_LINE_WIDTH+7)/8-1:0] data; // byte enable into data array
logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] vldrty; // bit enable into state array (valid for a pair of dirty/valid bits)
};
Expand Down Expand Up @@ -152,8 +152,8 @@ module std_nbdcache
// Miss Handling Unit
// ------------------
miss_handler #(
.CVA6Cfg (CVA6Cfg),
.NR_PORTS (NumPorts),
.CVA6Cfg(CVA6Cfg),
.NR_PORTS(NumPorts),
.axi_req_t(axi_req_t),
.axi_rsp_t(axi_rsp_t),
.cache_line_t(cache_line_t),
Expand Down
20 changes: 10 additions & 10 deletions core/cache_subsystem/wt_cache_subsystem.sv
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Expand Up @@ -23,18 +23,18 @@ module wt_cache_subsystem
import ariane_pkg::*;
import wt_cache_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type icache_areq_t = logic,
parameter type icache_arsp_t = logic,
parameter type icache_dreq_t = logic,
parameter type icache_drsp_t = logic,
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type icache_areq_t = logic,
parameter type icache_arsp_t = logic,
parameter type icache_dreq_t = logic,
parameter type icache_drsp_t = logic,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter type icache_req_t = logic,
parameter type icache_rtrn_t = logic,
parameter int unsigned NumPorts = 4,
parameter type noc_req_t = logic,
parameter type noc_resp_t = logic
parameter int unsigned NumPorts = 4,
parameter type noc_req_t = logic,
parameter type noc_resp_t = logic
) (
input logic clk_i,
input logic rst_ni,
Expand Down Expand Up @@ -145,7 +145,7 @@ module wt_cache_subsystem
// they have equal prio and are RR arbited
// Port 2 is write only and goes into the merging write buffer
wt_dcache #(
.CVA6Cfg (CVA6Cfg),
.CVA6Cfg(CVA6Cfg),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.dcache_req_t(dcache_req_t),
Expand Down Expand Up @@ -205,7 +205,7 @@ module wt_cache_subsystem
);
`else
wt_axi_adapter #(
.CVA6Cfg (CVA6Cfg),
.CVA6Cfg(CVA6Cfg),
.axi_req_t(noc_req_t),
.axi_rsp_t(noc_resp_t),
.dcache_req_t(dcache_req_t),
Expand Down
10 changes: 5 additions & 5 deletions core/cache_subsystem/wt_dcache.sv
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Expand Up @@ -128,10 +128,10 @@ module wt_dcache
///////////////////////////////////////////////////////

wt_dcache_missunit #(
.CVA6Cfg (CVA6Cfg),
.CVA6Cfg(CVA6Cfg),
.dcache_req_t(dcache_req_t),
.dcache_rtrn_t(dcache_rtrn_t),
.AmoTxId (RdAmoTxId),
.AmoTxId(RdAmoTxId),
.NumPorts(NumPorts)
) i_wt_dcache_missunit (
.clk_i (clk_i),
Expand Down Expand Up @@ -194,7 +194,7 @@ module wt_dcache
.CVA6Cfg(CVA6Cfg),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.RdTxId (RdAmoTxId)
.RdTxId(RdAmoTxId)
) i_wt_dcache_ctrl (
.clk_i (clk_i),
.rst_ni (rst_ni),
Expand Down Expand Up @@ -317,9 +317,9 @@ module wt_dcache
///////////////////////////////////////////////////////

wt_dcache_mem #(
.CVA6Cfg (CVA6Cfg),
.CVA6Cfg (CVA6Cfg),
.wbuffer_t(wbuffer_t),
.NumPorts(NumPorts)
.NumPorts (NumPorts)
) i_wt_dcache_mem (
.clk_i (clk_i),
.rst_ni (rst_ni),
Expand Down
2 changes: 1 addition & 1 deletion core/cache_subsystem/wt_dcache_ctrl.sv
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Expand Up @@ -20,7 +20,7 @@ module wt_dcache_ctrl
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type dcache_req_i_t = logic,
parameter type dcache_req_o_t = logic,
parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 1
parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 1
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
Expand Down
6 changes: 3 additions & 3 deletions core/cache_subsystem/wt_dcache_mem.sv
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Expand Up @@ -30,9 +30,9 @@ module wt_dcache_mem
import ariane_pkg::*;
import wt_cache_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type wbuffer_t = logic,
parameter int unsigned NumPorts = 3
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type wbuffer_t = logic,
parameter int unsigned NumPorts = 3
) (
input logic clk_i,
input logic rst_ni,
Expand Down
30 changes: 15 additions & 15 deletions core/cva6.sv
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Expand Up @@ -1205,21 +1205,21 @@ module cva6
// note: this only works with one cacheable region
// not as important since this cache subsystem is about to be
// deprecated
.CVA6Cfg (CVA6Cfg),
.icache_areq_t(icache_areq_t),
.icache_arsp_t(icache_arsp_t),
.icache_dreq_t(icache_dreq_t),
.icache_drsp_t(icache_drsp_t),
.CVA6Cfg (CVA6Cfg),
.icache_areq_t (icache_areq_t),
.icache_arsp_t (icache_arsp_t),
.icache_dreq_t (icache_dreq_t),
.icache_drsp_t (icache_drsp_t),
.icache_req_t (icache_req_t),
.icache_rtrn_t (icache_rtrn_t),
.dcache_req_i_t(dcache_req_i_t),
.dcache_req_o_t(dcache_req_o_t),
.NumPorts (NumPorts),
.axi_ar_chan_t(axi_ar_chan_t),
.axi_aw_chan_t(axi_aw_chan_t),
.axi_w_chan_t (axi_w_chan_t),
.axi_req_t (noc_req_t),
.axi_rsp_t (noc_resp_t)
.NumPorts (NumPorts),
.axi_ar_chan_t (axi_ar_chan_t),
.axi_aw_chan_t (axi_aw_chan_t),
.axi_w_chan_t (axi_w_chan_t),
.axi_req_t (noc_req_t),
.axi_rsp_t (noc_resp_t)
) i_cache_subsystem (
// to D$
.clk_i (clk_i),
Expand Down Expand Up @@ -1510,11 +1510,11 @@ module cva6
//RVFI INSTR

cva6_rvfi_probes #(
.CVA6Cfg (CVA6Cfg),
.exception_t (exception_t),
.CVA6Cfg (CVA6Cfg),
.exception_t (exception_t),
.scoreboard_entry_t(scoreboard_entry_t),
.lsu_ctrl_t (lsu_ctrl_t),
.rvfi_probes_t(rvfi_probes_t)
.lsu_ctrl_t (lsu_ctrl_t),
.rvfi_probes_t (rvfi_probes_t)
) i_cva6_rvfi_probes (

.flush_i (flush_ctrl_if),
Expand Down
4 changes: 2 additions & 2 deletions core/ex_stage.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -240,7 +240,7 @@ module ex_stage
assign alu_data = (alu_valid_i | branch_valid_i) ? fu_data_i : '0;

alu #(
.CVA6Cfg(CVA6Cfg),
.CVA6Cfg (CVA6Cfg),
.fu_data_t(fu_data_t)
) alu_i (
.clk_i,
Expand Down Expand Up @@ -346,7 +346,7 @@ module ex_stage
assign fpu_data = fpu_valid_i ? fu_data_i : '0;

fpu_wrap #(
.CVA6Cfg (CVA6Cfg),
.CVA6Cfg(CVA6Cfg),
.exception_t(exception_t),
.fu_data_t(fu_data_t)
) fpu_i (
Expand Down
8 changes: 4 additions & 4 deletions core/frontend/frontend.sv
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Expand Up @@ -455,10 +455,10 @@ module frontend
.clk_i,
.rst_ni,
.flush_bp_i(flush_bp_i),
.push_i (ras_push),
.pop_i (ras_pop),
.data_i (ras_update),
.data_o (ras_predict)
.push_i(ras_push),
.pop_i(ras_pop),
.data_i(ras_update),
.data_o(ras_predict)
);
end

Expand Down
2 changes: 1 addition & 1 deletion core/include/ariane_pkg.sv
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Expand Up @@ -723,7 +723,7 @@ package ariane_pkg;
riscv::xlen_t acc_cons_q;
riscv::pmpcfg_t [15:0] pmpcfg_q;
logic [15:0][riscv::PLEN-3:0] pmpaddr_q;
} rvfi_probes_csr_t;
} rvfi_probes_csr_t;

// RVFI CSR structure
typedef struct packed {
Expand Down
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