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expand glob port maps (#2585)
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Expands all glob port maps in the core/ directory of this repository except the core/cache_subsystem/ directory, despite the glob port maps in core/cache_subsystem/miss_handler.sv and core/cache_subsystem/std_nbdcache.sv.

Also reorders port maps to keep the same order as port declarations.
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@cathales
cathales authored Nov 7, 2024
1 parent 65285e5 commit 4619a67
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Showing 13 changed files with 220 additions and 136 deletions.
12 changes: 6 additions & 6 deletions core/acc_dispatcher.sv
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Expand Up @@ -302,18 +302,18 @@ module acc_dispatcher
assign acc_valid_o = acc_resp_i.resp_valid;
assign acc_exception_o = acc_resp_i.exception;
// Unpack the accelerator response
assign acc_fflags_valid_o = acc_resp_i.fflags_valid;
assign acc_fflags_o = acc_resp_i.fflags;
assign acc_fflags_valid_o = acc_resp_i.fflags_valid;
assign acc_fflags_o = acc_resp_i.fflags;
// Always ready to receive responses
assign acc_req_o.resp_ready = 1'b1;

// Signal dispatched load/store to issue stage
assign acc_ld_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_LOAD);
assign acc_st_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_STORE);
assign acc_ld_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_LOAD);
assign acc_st_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_STORE);

// Cache invalidation
assign inval_valid_o = acc_resp_i.inval_valid;
assign inval_addr_o = acc_resp_i.inval_addr;
assign inval_valid_o = acc_resp_i.inval_valid;
assign inval_addr_o = acc_resp_i.inval_addr;

/**************************
* Accelerator commit *
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10 changes: 5 additions & 5 deletions core/cache_subsystem/std_cache_subsystem.sv
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Expand Up @@ -193,7 +193,7 @@ module std_cache_subsystem
.flush_i (1'b0),
.testmode_i(1'b0),
.full_o (w_fifo_full),
.empty_o (), // leave open
.empty_o (), // leave open
.usage_o (w_fifo_usage),
.data_i (w_select),
// a new transaction was requested and granted
Expand All @@ -204,14 +204,14 @@ module std_cache_subsystem
.pop_i (w_fifo_pop)
);

always_ff @( posedge clk_i or negedge rst_ni ) begin : aw_lock_reg
always_ff @(posedge clk_i or negedge rst_ni) begin : aw_lock_reg
if (~rst_ni) aw_lock_q <= 1'b0;
else aw_lock_q <= aw_lock_d;
else aw_lock_q <= aw_lock_d;
end

assign w_fifo_push = ~aw_lock_q & axi_req_o.aw_valid;
assign w_fifo_pop = axi_req_o.w_valid & axi_resp_i.w_ready & axi_req_o.w.last;
assign aw_lock_d = ~axi_resp_i.aw_ready & (axi_req_o.aw_valid | aw_lock_q);
assign w_fifo_pop = axi_req_o.w_valid & axi_resp_i.w_ready & axi_req_o.w.last;
assign aw_lock_d = ~axi_resp_i.aw_ready & (axi_req_o.aw_valid | aw_lock_q);

// In fall-through mode, the empty_o will be low when push_i is high (on zero usage).
// We do not want this here. Also, usage_o is missing the MSB, so on full fifo, usage_o is zero.
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14 changes: 7 additions & 7 deletions core/cache_subsystem/tag_cmp.sv
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Expand Up @@ -85,13 +85,13 @@ module tag_cmp #(

`ifndef SYNTHESIS
`ifndef VERILATOR
// assert that cache only hits on one way
// this only needs to be checked one cycle after all ways have been requested
onehot :
assert property (@(posedge clk_i) disable iff (!rst_ni) &req_i |=> $onehot0(hit_way_o))
else begin
$fatal(1, "Hit should be one-hot encoded");
end
// assert that cache only hits on one way
// this only needs to be checked one cycle after all ways have been requested
onehot :
assert property (@(posedge clk_i) disable iff (!rst_ni) &req_i |=> $onehot0(hit_way_o))
else begin
$fatal(1, "Hit should be one-hot encoded");
end
`endif
`endif

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6 changes: 4 additions & 2 deletions core/commit_stage.sv
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Expand Up @@ -60,10 +60,10 @@ module commit_stage
output logic [CVA6Cfg.XLEN-1:0] csr_wdata_o,
// Data to read from CSR - CSR_REGFILE
input logic [CVA6Cfg.XLEN-1:0] csr_rdata_i,
// Exception or interrupt occurred in CSR stage (the same as commit) - CSR_REGFILE
input exception_t csr_exception_i,
// Write the fflags CSR - CSR_REGFILE
output logic csr_write_fflags_o,
// Exception or interrupt occurred in CSR stage (the same as commit) - CSR_REGFILE
input exception_t csr_exception_i,
// Commit the pending store - EX_STAGE
output logic commit_lsu_o,
// Commit buffer of LSU is ready - EX_STAGE
Expand All @@ -84,7 +84,9 @@ module commit_stage
output logic flush_commit_o,
// Flush TLBs and pipeline - CONTROLLER
output logic sfence_vma_o,
// TO_BE_COMPLETED - CONTROLLER
output logic hfence_vvma_o,
// TO_BE_COMPLETED - CONTROLLER
output logic hfence_gvma_o
);

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4 changes: 4 additions & 0 deletions core/controller.sv
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Expand Up @@ -45,7 +45,9 @@ module controller
input logic flush_dcache_ack_i,
// Flush TLBs - EX_STAGE
output logic flush_tlb_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output logic flush_tlb_vvma_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output logic flush_tlb_gvma_o,
// Halt request from CSR (WFI instruction) - CSR_REGFILE
input logic halt_csr_i,
Expand All @@ -69,7 +71,9 @@ module controller
input logic fence_i,
// We got an instruction to flush the TLBs and pipeline - COMMIT_STAGE
input logic sfence_vma_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic hfence_vvma_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic hfence_gvma_i,
// Flush request from commit stage - COMMIT_STAGE
input logic flush_commit_i,
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2 changes: 0 additions & 2 deletions core/csr_regfile.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,6 @@ module csr_regfile
input logic [CVA6Cfg.VLEN-1:0] boot_addr_i,
// Hart id in a multicore environment (reflected in a CSR) - SUBSYSTEM
input logic [CVA6Cfg.XLEN-1:0] hart_id_i,
// we are taking an exception
// We've got an exception from the commit stage, take it - COMMIT_STAGE
input exception_t ex_i,
// Operation to perform on the CSR file - COMMIT_STAGE
Expand Down Expand Up @@ -153,7 +152,6 @@ module csr_regfile
output logic dcache_en_o,
// Accelerator memory consistent mode - ACC_DISPATCHER
output logic acc_cons_en_o,
// Performance Counter
// read/write address to performance counter module - PERF_COUNTERS
output logic [11:0] perf_addr_o,
// write data to performance counter module - PERF_COUNTERS
Expand Down
119 changes: 59 additions & 60 deletions core/cva6.sv
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Expand Up @@ -643,25 +643,26 @@ module cva6
.icache_dreq_t(icache_dreq_t),
.icache_drsp_t(icache_drsp_t)
) i_frontend (
.flush_i (flush_ctrl_if), // not entirely correct
.clk_i,
.rst_ni,
.boot_addr_i (boot_addr_i[CVA6Cfg.VLEN-1:0]),
.flush_bp_i (1'b0),
.flush_i (flush_ctrl_if), // not entirely correct
.halt_i (halt_ctrl),
.debug_mode_i (debug_mode),
.boot_addr_i (boot_addr_i[CVA6Cfg.VLEN-1:0]),
.icache_dreq_i (icache_dreq_cache_if),
.icache_dreq_o (icache_dreq_if_cache),
.resolved_branch_i (resolved_branch),
.pc_commit_i (pc_commit),
.set_pc_commit_i (set_pc_ctrl_pcgen),
.set_debug_pc_i (set_debug_pc),
.epc_i (epc_commit_pcgen),
.pc_commit_i (pc_commit),
.ex_valid_i (ex_commit.valid),
.resolved_branch_i (resolved_branch),
.eret_i (eret),
.epc_i (epc_commit_pcgen),
.trap_vector_base_i (trap_vector_base_commit_pcgen),
.ex_valid_i (ex_commit.valid),
.set_debug_pc_i (set_debug_pc),
.debug_mode_i (debug_mode),
.icache_dreq_o (icache_dreq_if_cache),
.icache_dreq_i (icache_dreq_cache_if),
.fetch_entry_o (fetch_entry_if_id),
.fetch_entry_valid_o(fetch_valid_if_id),
.fetch_entry_ready_i(fetch_ready_id_if),
.*
.fetch_entry_ready_i(fetch_ready_id_if)
);

// ---------
Expand Down Expand Up @@ -857,8 +858,8 @@ module cva6
.issue_instr_o (issue_instr_id_acc),
.issue_instr_hs_o (issue_instr_hs_id_acc),
// Commit
.resolved_branch_i (resolved_branch),
.trans_id_i (trans_id_ex_id),
.resolved_branch_i (resolved_branch),
.wbdata_i (wbdata_ex_id),
.ex_ex_i (ex_ex_ex_id),
.wt_valid_i (wt_valid_ex_id),
Expand All @@ -876,8 +877,7 @@ module cva6
.stall_issue_o (stall_issue),
//RVFI
.rvfi_issue_pointer_o (rvfi_issue_pointer),
.rvfi_commit_pointer_o(rvfi_commit_pointer),
.*
.rvfi_commit_pointer_o(rvfi_commit_pointer)
);

// ---------
Expand Down Expand Up @@ -1043,30 +1043,29 @@ module cva6
.commit_drop_i (commit_drop_id_commit),
.commit_ack_o (commit_ack_commit_id),
.commit_macro_ack_o(commit_macro_ack),
.no_st_pending_i (no_st_pending_commit),
.waddr_o (waddr_commit_id),
.wdata_o (wdata_commit_id),
.we_gpr_o (we_gpr_commit_id),
.we_fpr_o (we_fpr_commit_id),
.commit_lsu_o (lsu_commit_commit_ex),
.commit_lsu_ready_i(lsu_commit_ready_ex_commit),
.commit_tran_id_o (lsu_commit_trans_id),
.amo_valid_commit_o(amo_valid_commit),
.amo_resp_i (amo_resp),
.commit_csr_o (csr_commit_commit_ex),
.pc_o (pc_commit),
.csr_op_o (csr_op_commit_csr),
.csr_wdata_o (csr_wdata_commit_csr),
.csr_rdata_i (csr_rdata_csr_commit),
.csr_write_fflags_o(csr_write_fflags_commit_cs),
.csr_exception_i (csr_exception_csr_commit),
.commit_lsu_o (lsu_commit_commit_ex),
.commit_lsu_ready_i(lsu_commit_ready_ex_commit),
.commit_tran_id_o (lsu_commit_trans_id),
.amo_valid_commit_o(amo_valid_commit),
.no_st_pending_i (no_st_pending_commit),
.commit_csr_o (csr_commit_commit_ex),
.fence_i_o (fence_i_commit_controller),
.fence_o (fence_commit_controller),
.flush_commit_o (flush_commit),
.sfence_vma_o (sfence_vma_commit_controller),
.hfence_vvma_o (hfence_vvma_commit_controller),
.hfence_gvma_o (hfence_gvma_commit_controller),
.flush_commit_o (flush_commit),
.*
.hfence_gvma_o (hfence_gvma_commit_controller)
);

assign commit_ack = commit_macro_ack & ~commit_drop_id_commit;
Expand All @@ -1082,6 +1081,9 @@ module cva6
.rvfi_probes_csr_t (rvfi_probes_csr_t),
.MHPMCounterNum (MHPMCounterNum)
) csr_regfile_i (
.clk_i,
.rst_ni,
.time_irq_i,
.flush_o (flush_csr_ctrl),
.halt_csr_o (halt_csr_ctrl),
.commit_instr_i (commit_instr_id_commit),
Expand All @@ -1090,17 +1092,16 @@ module cva6
.hart_id_i (hart_id_i[CVA6Cfg.XLEN-1:0]),
.ex_i (ex_commit),
.csr_op_i (csr_op_commit_csr),
.csr_write_fflags_i (csr_write_fflags_commit_cs),
.dirty_fp_state_i (dirty_fp_state),
.dirty_v_state_i (dirty_v_state),
.csr_addr_i (csr_addr_ex_csr),
.csr_wdata_i (csr_wdata_commit_csr),
.csr_rdata_o (csr_rdata_csr_commit),
.dirty_fp_state_i (dirty_fp_state),
.csr_write_fflags_i (csr_write_fflags_commit_cs),
.dirty_v_state_i (dirty_v_state),
.pc_i (pc_commit),
.csr_exception_o (csr_exception_csr_commit),
.epc_o (epc_commit_pcgen),
.eret_o (eret),
.set_debug_pc_o (set_debug_pc),
.trap_vector_base_o (trap_vector_base_commit_pcgen),
.priv_lvl_o (priv_lvl),
.v_o (v),
Expand All @@ -1113,13 +1114,13 @@ module cva6
.fprec_o (fprec_csr_ex),
.vs_o (vs),
.irq_ctrl_o (irq_ctrl_csr_id),
.ld_st_priv_lvl_o (ld_st_priv_lvl_csr_ex),
.ld_st_v_o (ld_st_v_csr_ex),
.csr_hs_ld_st_inst_i (csr_hs_ld_st_inst_ex),
.en_translation_o (enable_translation_csr_ex),
.en_g_translation_o (enable_g_translation_csr_ex),
.en_ld_st_translation_o (en_ld_st_translation_csr_ex),
.en_ld_st_g_translation_o(en_ld_st_g_translation_csr_ex),
.ld_st_priv_lvl_o (ld_st_priv_lvl_csr_ex),
.ld_st_v_o (ld_st_v_csr_ex),
.csr_hs_ld_st_inst_i (csr_hs_ld_st_inst_ex),
.sum_o (sum_csr_ex),
.vs_sum_o (vs_sum_csr_ex),
.mxr_o (mxr_csr_ex),
Expand All @@ -1130,15 +1131,19 @@ module cva6
.vs_asid_o (vs_asid_csr_ex),
.hgatp_ppn_o (hgatp_ppn_csr_ex),
.vmid_o (vmid_csr_ex),
.irq_i,
.ipi_i,
.debug_req_i,
.set_debug_pc_o (set_debug_pc),
.tvm_o (tvm_csr_id),
.tw_o (tw_csr_id),
.vtw_o (vtw_csr_id),
.tsr_o (tsr_csr_id),
.hu_o (hu),
.debug_mode_o (debug_mode),
.single_step_o (single_step_csr_commit),
.dcache_en_o (dcache_en_csr_nbdcache),
.icache_en_o (icache_en_csr),
.dcache_en_o (dcache_en_csr_nbdcache),
.acc_cons_en_o (acc_cons_en_csr),
.perf_addr_o (addr_csr_perf),
.perf_data_o (data_csr_perf),
Expand All @@ -1148,12 +1153,7 @@ module cva6
.pmpaddr_o (pmpaddr),
.mcountinhibit_o (mcountinhibit_csr_perf),
//RVFI
.rvfi_csr_o (rvfi_csr),
.debug_req_i,
.ipi_i,
.irq_i,
.time_irq_i,
.*
.rvfi_csr_o (rvfi_csr)
);

// ------------------------
Expand Down Expand Up @@ -1211,40 +1211,39 @@ module cva6
.CVA6Cfg(CVA6Cfg),
.bp_resolve_t(bp_resolve_t)
) controller_i (
.clk_i,
.rst_ni,
// virtualization mode
.v_i (v),
// flush ports
.set_pc_commit_o (set_pc_ctrl_pcgen),
.flush_unissued_instr_o(flush_unissued_instr_ctrl_id),
.flush_if_o (flush_ctrl_if),
.flush_unissued_instr_o(flush_unissued_instr_ctrl_id),
.flush_id_o (flush_ctrl_id),
.flush_ex_o (flush_ctrl_ex),
.flush_bp_o (flush_ctrl_bp),
.flush_icache_o (icache_flush_ctrl_cache),
.flush_dcache_o (dcache_flush_ctrl_cache),
.flush_dcache_ack_i (dcache_flush_ack_cache_ctrl),
.flush_tlb_o (flush_tlb_ctrl_ex),
.flush_tlb_vvma_o (flush_tlb_vvma_ctrl_ex),
.flush_tlb_gvma_o (flush_tlb_gvma_ctrl_ex),
.flush_dcache_o (dcache_flush_ctrl_cache),
.flush_dcache_ack_i (dcache_flush_ack_cache_ctrl),

.halt_csr_i (halt_csr_ctrl),
.halt_acc_i (halt_acc_ctrl),
.halt_o (halt_ctrl),
.halt_csr_i (halt_csr_ctrl),
.halt_acc_i (halt_acc_ctrl),
.halt_o (halt_ctrl),
// control ports
.eret_i (eret),
.ex_valid_i (ex_commit.valid),
.set_debug_pc_i (set_debug_pc),
.flush_csr_i (flush_csr_ctrl),
.resolved_branch_i(resolved_branch),
.fence_i_i (fence_i_commit_controller),
.fence_i (fence_commit_controller),
.sfence_vma_i (sfence_vma_commit_controller),
.hfence_vvma_i (hfence_vvma_commit_controller),
.hfence_gvma_i (hfence_gvma_commit_controller),
.flush_commit_i (flush_commit),
.flush_acc_i (flush_acc),

.flush_icache_o(icache_flush_ctrl_cache),
.*
.eret_i (eret),
.ex_valid_i (ex_commit.valid),
.set_debug_pc_i (set_debug_pc),
.resolved_branch_i (resolved_branch),
.flush_csr_i (flush_csr_ctrl),
.fence_i_i (fence_i_commit_controller),
.fence_i (fence_commit_controller),
.sfence_vma_i (sfence_vma_commit_controller),
.hfence_vvma_i (hfence_vvma_commit_controller),
.hfence_gvma_i (hfence_gvma_commit_controller),
.flush_commit_i (flush_commit),
.flush_acc_i (flush_acc)
);

// -------------------
Expand Down
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