Merge branch 'master' into jquevremont-resources

.gitlab-ci.yml

@@ -131,8 +131,8 @@ build_tools:
     - echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC
 
 .simu_after_script: &simu_after_script
-  - for i in $(find verif/sim/out*/[vq]*_sim -type f \( -name "*.csv" -o -name "*.iss" -o -name "*.yaml" \)) ; do head -10000 $i > artifacts/logs/$(basename $i).head ; done
-  - head -10000 verif/sim/logfile.log > artifacts/logs/logfile.log.head
+  - for i in $(find verif/sim/out*/[vq]*_sim -type f \( -name "*.csv" -o -name "*.iss" -o -name "*.yaml" \)) ; do tail -10000 $i > artifacts/logs/$(basename $i) ; done
+  - tail -10000 verif/sim/logfile.log > artifacts/logs/logfile.log
   - if [ -n "$SPIKE_TANDEM" ]; then python3 .gitlab-ci/scripts/report_tandem.py verif/sim/out*/"$DV_SIMULATORS"_sim; else python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log; fi
 
 smoke-tests:
@@ -175,7 +175,7 @@ smoke-bench:
   extends:
     - .fe_smoke_test
   variables:
-    DASHBOARD_JOB_TITLE: "smoke-bench"
+    DASHBOARD_JOB_TITLE: "smoke-bench $DV_TARGET"
     DASHBOARD_JOB_DESCRIPTION: "Performance indicator"
     DASHBOARD_SORT_INDEX: 5
     DASHBOARD_JOB_CATEGORY: "Performance"
@@ -275,6 +275,7 @@ asic-synthesis:
     - echo $DV_TARGET
     - source ./verif/sim/setup-env.sh
     - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b ${SYNTH_SCRIPT_BRANCH}
+    - git -C ${SYNTH_SCRIPT_PATH} checkout cce5ea41
     - cp -r ${SYNTH_SCRIPT_PATH}/cva6/ ../
     - git apply ${SYNTH_SCRIPT_PATH}/patches/*.patch
     - echo $SYN_DCSHELL_BASHRC; source $SYN_DCSHELL_BASHRC
@@ -356,6 +357,7 @@ riscv_arch_test:
   after_script: *simu_after_script
 
 compliance:
+  timeout : 2 hours
   extends:
     - .regress_test
   variables:
@@ -377,7 +379,7 @@ riscv-tests-v:
     DASHBOARD_JOB_DESCRIPTION: "Riscv-test regression suite (virtual)"
     DASHBOARD_SORT_INDEX: 3
     DASHBOARD_JOB_CATEGORY: "Test suites"
-    DV_SIMULATORS: "vcs-testharness,spike"
+    DV_SIMULATORS: "veri-testharness,spike"
     DV_TARGET: cv64a6_imafdc_sv39
     DV_TESTLISTS: "../tests/testlist_riscv-tests-$DV_TARGET-v.yaml"
   script: source verif/regress/dv-riscv-tests.sh
@@ -543,8 +545,8 @@ simu-gate:
     - !reference [.copy_spike_artifacts]
     - echo $PERIOD
     - source ./verif/sim/setup-env.sh
-    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b testelf
-    - git -C ${SYNTH_SCRIPT_PATH} checkout cb92f846
+    - git clone ${SYNTH_SCRIPT} ${SYNTH_SCRIPT_PATH} -b ${SYNTH_SCRIPT_BRANCH}
+    - git -C ${SYNTH_SCRIPT_PATH} checkout cce5ea41
     - cp -r ${SYNTH_SCRIPT_PATH}/cva6/ ../
     - git apply ${SYNTH_SCRIPT_PATH}/patches/*.patch
     - source verif/regress/install-riscv-tests.sh

.gitlab-ci/expected_synth.yml

@@ -1,2 +1,2 @@
 cv32a65x:
-  gates: 178869
+  gates: 187456

.gitlab-ci/scripts/report_benchmark.py

@@ -19,12 +19,12 @@
 # Keep it up-to-date with compiler version and core performance improvements
 # Will fail if the number of cycles is different from this one
 valid_cycles = {
-    "dhrystone_dual": 20199,
-    "dhrystone_single": 25019,
-    "coremark_dual": 1017451,
-    "coremark_single": 1308656,
-    "dhrystone_cv32a65x": 32566,
-    "dhrystone_cv32a60x": 39994,
+    "dhrystone_dual": 18935,
+    "dhrystone_single": 24127,
+    "coremark_dual": 1001191,
+    "coremark_single": 1300030,
+    "dhrystone_cv32a65x": 31976,
+    "dhrystone_cv32a60x": 39449,
 }
 
 for arg in sys.argv[1:]:

.gitlab-ci/scripts/report_simu.py

@@ -18,7 +18,7 @@
 with_logs = os.environ.get("COLLECT_SIMU_LOGS") != None
 
 pattern = re.compile(
-    r'(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO     )(?:Processing regression test list : (?:.*)/testlist_(.*-.*)(?:.yaml), test: (\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO     )Compiling (.*):.*$|Compiling (.*): .*(tests\S*))$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO     )Found matching ISS: (\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO     )Target: (\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2}(?: INFO     ))ISA (\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} (?:(?:INFO     )\[(\w*)\]: (\d*) matched(?:, (\d*) mismatch)?)|(?:^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2})(?: ERROR    )(\D{5})(?:.*)$))',
+    r'(?:.*Compiling test: (.*))$[\s\S]*?(?:^.*Target: (.*)$)$[\s\S]*?(?:^.*ISA (.*)$)[\s\S]*?(?:^.*Found matching ISS: (.*)$)[\s\S]*?(?:^.*\[(PASSED|FAILED)\].*$)',
     re.MULTILINE)
 list_of_tests = pattern.findall(log)
 
@@ -27,7 +27,6 @@
 metric.add_column("TARGET", "text")
 metric.add_column("ISA", "text")
 metric.add_column("TEST", "text")
-metric.add_column("TEST LIST", "text")
 
 if with_logs:
     metric.add_column("OUTPUT", "log")
@@ -40,22 +39,20 @@
 for i in list_of_tests:
     job_test_total += 1
 
-    target = i[6]
-    isa = i[7]
-    test = i[1] or i[4].split("/")[-1].split(".")[0]
-    testsuite = i[0] or "custom test"
-    test_type = i[2] or i[4]
+    target = i[1]
+    isa = i[2]
+    test = i[0] 
 
     if with_logs:
         logsPath = "logs/" + os.environ.get("CI_JOB_ID") + "/artifacts/logs/"
-        output_log = logsPath + 'logfile.log.head'
-        tb_log = logsPath + test + "." + target + '.log.iss.head'
-        disassembly = logsPath + test + "." + target + '.csv.head'
-        col = [target, isa, test, testsuite, output_log, tb_log, disassembly]
+        output_log = logsPath + 'logfile.log'
+        tb_log = logsPath + test + "." + target + '.log.iss'
+        disassembly = logsPath + test + "." + target + '.csv'
+        col = [target, isa, test, output_log, tb_log, disassembly]
     else:
-        col = [target, isa, test, testsuite]
+        col = [target, isa, test]
 
-    if i[8] == "PASSED":
+    if i[4] == "PASSED":
         metric.add_pass(*col)
         job_test_pass += 1
     else:

.gitlab-ci/scripts/report_tandem.py

@@ -47,6 +47,7 @@ def add_table_legend(metrics_table, with_logs):
 
     if with_logs:
         metrics_table.add_column("OUTPUT", "log")
+        metrics_table.add_column("TANDEM REPORT", "log")
         metrics_table.add_column("TB LOGS", "log")
         metrics_table.add_column("DISASSEMBLY", "log")
 
@@ -74,13 +75,15 @@ def add_test_row(report_file, metrics_table, with_logs):
 
         if with_logs:
             logs_path = "logs/" + os.environ.get("CI_JOB_ID") + "/artifacts/logs/"
-            output_log = logs_path + "logfile.log.head"
+            output_log = logs_path + "logfile.log"
             log_prefix = logs_path + report['test'] + "_" + str(report["iteration"]) + "." + report["target"] \
                 if "iteration" in report else logs_path + report['test'] + "." + report["target"]
-            tb_log = log_prefix + '.log.iss.head'
-            disassembly = log_prefix + '.log.csv.head'
+            tb_log = log_prefix + '.log.iss'
+            disassembly = log_prefix + '.log.csv'
+            tandem_report = log_prefix + '.log.yaml'
 
             row.append(output_log)
+            row.append(tandem_report)
             row.append(tb_log)
             row.append(disassembly)
 

.gitmodules

@@ -49,3 +49,9 @@
 [submodule "docs/06_cv32a65x_riscv/riscv-isa-manual"]
 	path = docs/riscv-isa/riscv-isa-manual
 	url = https://github.com/riscv/riscv-isa-manual.git
+[submodule "corev_apu/fpga/src/apb"]
+	path = corev_apu/fpga/src/apb
+	url = https://github.com/pulp-platform/apb.git
+[submodule "corev_apu/fpga/src/gpio"]
+	path = corev_apu/fpga/src/gpio
+	url = https://github.com/pulp-platform/gpio.git

.readthedocs.yaml

@@ -4,17 +4,28 @@
 
 version: 2
 
+submodules:
+  include:
+    - docs/riscv-isa/riscv-isa-manual
+
 build:
   os: "ubuntu-20.04"
   tools:
     python: "3.9"
     nodejs: "20"
     ruby: "3.3"
+  apt_packages:
+    - cmake
+    - bison
+    - flex
+    - libpango1.0-dev
+    - libgdk-pixbuf2.0-0
+    - libgtk2.0-dev
   jobs:
-    post-install:
+    post_install:
       - npm install docs/riscv-isa/riscv-isa-manual/dependencies
       - gem install -g docs/riscv-isa/riscv-isa-manual/dependencies/Gemfile
-    pre-build:
+    pre_build:
       - make -C docs prepare
 
 # Build from the docs directory with Sphinx

Flist.ariane

@@ -160,6 +160,7 @@ vendor/openhwgroup/cvfpu/src/fpnew_rounding.sv
 vendor/openhwgroup/cvfpu/src/fpnew_top.sv
 core/pmp/src/pmp.sv
 core/pmp/src/pmp_entry.sv
+core/pmp/src/pmp_data_if.sv
 common/local/util/instr_tracer.sv
 core/cvxif_example/cvxif_example_coprocessor.sv
 core/cvxif_example/instr_decoder.sv

README.md

@@ -1,4 +1,4 @@
-# CVA6 RISC-V CPU [![Build Status](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml/badge.svg?branch=master)](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml) [![CVA6 dashboard](https://riscv-ci.pages.thales-invia.fr/dashboard/badge.svg)](https://riscv-ci.pages.thales-invia.fr/dashboard/) [![GitHub release](https://img.shields.io/github/release/openhwgroup/cva6?include_prereleases=&sort=semver&color=blue)](https://github.com/openhwgroup/cva6/releases/)
+# CVA6 RISC-V CPU [![Build Status](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml/badge.svg?branch=master)](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml) [![CVA6 dashboard](https://riscv-ci.pages.thales-invia.fr/dashboard/badge.svg)](https://riscv-ci.pages.thales-invia.fr/dashboard/) [![Documentation Status](https://readthedocs.com/projects/openhw-group-cva6-user-manual/badge/?version=latest)](https://docs.openhwgroup.org/projects/cva6-user-manual/?badge=latest) [![GitHub release](https://img.shields.io/github/release/openhwgroup/cva6?include_prereleases=&sort=semver&color=blue)](https://github.com/openhwgroup/cva6/releases/)
 
 CVA6 is a 6-stage, single-issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M, A and C extensions as specified in Volume I: User-Level ISA V 2.3 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore, it is compliant to the draft external debug spec 0.13.
 

config/gen_from_riscv_config/cv32a65x/csr/csr.adoc

@@ -334,7 +334,7 @@ Description:: Physical memory protection address register
 |===
 | Bits | Field Name | Reset Value | Type | Legal Values | Description
 
-| [31:0] | PMPADDR[I] | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | Physical memory protection address register 
+| [31:0] | PMPADDR[I] | 0x00000000 | WARL | masked: & 0xFFFFFFFE \| 0x0 | Physical memory protection address register 
 |===
 
 [[_PMPADDR8-63]]

config/gen_from_riscv_config/cv32a65x/csr/csr.rst

@@ -418,13 +418,13 @@ PMPCFG[0-1]
 +---------+----------------+---------------+--------+----------------------+------------------------+
 | Bits    | Field Name     | Reset Value   | Type   | Legal Values         | Description            |
 +=========+================+===============+========+======================+========================+
-| [7:0]   | PMP[I*4 +0]CFG | 0x0           | WARL   | masked: & 0x8f | 0x0 | pmp configuration bits |
+| [7:0]   | PMP[I*4 +0]CFG | 0x0           | WARL   | masked: & 0x8f \| 0x0 | pmp configuration bits |
 +---------+----------------+---------------+--------+----------------------+------------------------+
-| [15:8]  | PMP[I*4 +1]CFG | 0x0           | WARL   | masked: & 0x8f | 0x0 | pmp configuration bits |
+| [15:8]  | PMP[I*4 +1]CFG | 0x0           | WARL   | masked: & 0x8f \| 0x0 | pmp configuration bits |
 +---------+----------------+---------------+--------+----------------------+------------------------+
-| [23:16] | PMP[I*4 +2]CFG | 0x0           | WARL   | masked: & 0x8f | 0x0 | pmp configuration bits |
+| [23:16] | PMP[I*4 +2]CFG | 0x0           | WARL   | masked: & 0x8f \| 0x0 | pmp configuration bits |
 +---------+----------------+---------------+--------+----------------------+------------------------+
-| [31:24] | PMP[I*4 +3]CFG | 0x0           | WARL   | masked: & 0x8f | 0x0 | pmp configuration bits |
+| [31:24] | PMP[I*4 +3]CFG | 0x0           | WARL   | masked: & 0x8f \| 0x0 | pmp configuration bits |
 +---------+----------------+---------------+--------+----------------------+------------------------+
 
 
@@ -462,7 +462,7 @@ PMPADDR[0-7]
 +--------+--------------+---------------+--------+-------------------------+---------------------------------------------+
 | Bits   | Field Name   | Reset Value   | Type   | Legal Values            | Description                                 |
 +========+==============+===============+========+=========================+=============================================+
-| [31:0] | PMPADDR[I]   | 0x00000000    | WARL   | 0x00000000 - 0xFFFFFFFF | Physical memory protection address register |
+| [31:0] | PMPADDR[I]   | 0x00000000    | WARL   | masked: & 0xFFFFFFFE \| 0x00000000 | Physical memory protection address register |
 +--------+--------------+---------------+--------+-------------------------+---------------------------------------------+
 
 

config/gen_from_riscv_config/cv32a65x/spike/spike.yaml

@@ -44,6 +44,14 @@ spike_param_tree:
       tdata2_accessible: 0
       tdata3_accessible: 0
       tselect_accessible: 0
+      pmpaddr0_write_mask: 0xFFFFFFFE
+      pmpaddr1_write_mask: 0xFFFFFFFE
+      pmpaddr2_write_mask: 0xFFFFFFFE
+      pmpaddr3_write_mask: 0xFFFFFFFE
+      pmpaddr4_write_mask: 0xFFFFFFFE
+      pmpaddr5_write_mask: 0xFFFFFFFE
+      pmpaddr6_write_mask: 0xFFFFFFFE
+      pmpaddr7_write_mask: 0xFFFFFFFE
       mhartid: 0
       mvendorid_override_mask : 0xFFFFFFFF
       mvendorid_override_value: 1538

config/riscv-config/cv32a65x/generated/isa_gen.yaml

@@ -3165,7 +3165,7 @@ hart0:
                 warl:
                     dependency_fields: []
                     legal:
-                      - pmpaddr0[31:0] in [0x00000000:0xFFFFFFFF]
+                      - pmpaddr0[31:0] bitmask [0xFFFFFFFE, 0x00000000]
                     wr_illegal:
                       - unchanged
             fields: []
@@ -3186,7 +3186,7 @@ hart0:
                 warl:
                     dependency_fields: []
                     legal:
-                      - pmpaddr1[31:0] in [0x00000000:0xFFFFFFFF]
+                      - pmpaddr1[31:0] bitmask [0xFFFFFFFE, 0x00000000]
                     wr_illegal:
                       - unchanged
             fields: []
@@ -3207,7 +3207,7 @@ hart0:
                 warl:
                     dependency_fields: []
                     legal:
-                      - pmpaddr2[31:0] in [0x00000000:0xFFFFFFFF]
+                      - pmpaddr2[31:0] bitmask [0xFFFFFFFE, 0x00000000]
                     wr_illegal:
                       - unchanged
             fields: []
@@ -3228,7 +3228,7 @@ hart0:
                 warl:
                     dependency_fields: []
                     legal:
-                      - pmpaddr3[31:0] in [0x00000000:0xFFFFFFFF]
+                      - pmpaddr3[31:0] bitmask [0xFFFFFFFE, 0x00000000]
                     wr_illegal:
                       - unchanged
             fields: []
@@ -3249,7 +3249,7 @@ hart0:
                 warl:
                     dependency_fields: []
                     legal:
-                      - pmpaddr4[31:0] in [0x00000000:0xFFFFFFFF]
+                      - pmpaddr4[31:0] bitmask [0xFFFFFFFE, 0x00000000]
                     wr_illegal:
                       - unchanged
             fields: []
@@ -3270,7 +3270,7 @@ hart0:
                 warl:
                     dependency_fields: []
                     legal:
-                      - pmpaddr5[31:0] in [0x00000000:0xFFFFFFFF]
+                      - pmpaddr5[31:0] bitmask [0xFFFFFFFE, 0x00000000]
                     wr_illegal:
                       - unchanged
             fields: []
@@ -3291,7 +3291,7 @@ hart0:
                 warl:
                     dependency_fields: []
                     legal:
-                      - pmpaddr6[31:0] in [0x00000000:0xFFFFFFFF]
+                      - pmpaddr6[31:0] bitmask [0xFFFFFFFE, 0x00000000]
                     wr_illegal:
                       - unchanged
             fields: []
@@ -3312,7 +3312,7 @@ hart0:
                 warl:
                     dependency_fields: []
                     legal:
-                      - pmpaddr7[31:0] in [0x00000000:0xFFFFFFFF]
+                      - pmpaddr7[31:0] bitmask [0xFFFFFFFE, 0x00000000]
                     wr_illegal:
                       - unchanged
             fields: []