Code coverage: Add NonIdemPotence parameter (#1647)

core/cache_subsystem/cva6_icache.sv

@@ -255,7 +255,7 @@ module cva6_icache
         // readout speculatively
         cache_rden  = cache_en_q;
 
-        if (areq_i.fetch_valid && (!dreq_i.spec || !addr_ni)) begin
+        if (areq_i.fetch_valid && (!dreq_i.spec || ((CVA6Cfg.NonIdemPotenceEn && !addr_ni) || (!CVA6Cfg.NonIdemPotenceEn)))) begin
           // check if we have to flush
           if (flush_d) begin
             state_d = IDLE;

core/cache_subsystem/wt_dcache_wbuffer.sv

@@ -437,7 +437,7 @@ module wt_dcache_wbuffer
 
   logic ni_inside, ni_conflict;
   assign ni_inside = |ni_pending_q;
-  assign ni_conflict = is_ni && ni_inside;
+  assign ni_conflict = CVA6Cfg.NonIdemPotenceEn && is_ni && ni_inside;
   assign not_ni_o = !ni_inside;
   assign empty_o    = !(|valid);
 

core/cva6.sv

@@ -163,6 +163,8 @@ module cva6
 
   localparam NrRgprPorts = 2;
 
+  localparam bit NonIdemPotenceEn = CVA6Cfg.NrNonIdempotentRules && CVA6Cfg.NonIdempotentLength;  // Currently only used by V extension (Ara)
+
   localparam config_pkg::cva6_cfg_t CVA6ExtendCfg = {
     CVA6Cfg.NrCommitPorts,
     CVA6Cfg.AxiAddrWidth,
@@ -214,7 +216,8 @@ module cva6
     CVA6Cfg.CachedRegionAddrBase,
     CVA6Cfg.CachedRegionLength,
     CVA6Cfg.MaxOutstandingStores,
-    CVA6Cfg.DebugEn
+    CVA6Cfg.DebugEn,
+    NonIdemPotenceEn
   };
 
 

core/include/config_pkg.sv

@@ -112,6 +112,7 @@ package config_pkg;
     /// Maximum number of outstanding stores.
     int unsigned                 MaxOutstandingStores;
     bit                          DebugEn;
+    bit                          NonIdemPotenceEn;
   } cva6_cfg_t;
 
 

core/include/cv32a60x_config_pkg.sv

@@ -138,7 +138,8 @@ package cva6_config_pkg;
       CachedRegionAddrBase: 1024'({64'h8000_0000}),
       CachedRegionLength: 1024'({64'h40000000}),
       MaxOutstandingStores: unsigned'(7),
-      DebugEn: bit'(1)
+      DebugEn: bit'(1),
+      NonIdemPotenceEn: bit'(0)
   };
 
 endpackage

core/include/cv32a6_embedded_config_pkg.sv

@@ -137,7 +137,8 @@ package cva6_config_pkg;
       CachedRegionAddrBase: 1024'({64'h8000_0000}),
       CachedRegionLength: 1024'({64'h40000000}),
       MaxOutstandingStores: unsigned'(7),
-      DebugEn: bit'(0)
+      DebugEn: bit'(0),
+      NonIdemPotenceEn: bit'(0)
   };
 
 endpackage

core/include/cv32a6_ima_sv32_fpga_config_pkg.sv

@@ -138,7 +138,8 @@ package cva6_config_pkg;
       CachedRegionAddrBase: 1024'({64'h8000_0000}),
       CachedRegionLength: 1024'({64'h40000000}),
       MaxOutstandingStores: unsigned'(7),
-      DebugEn: bit'(1)
+      DebugEn: bit'(1),
+      NonIdemPotenceEn: bit'(0)
   };
 
 endpackage

core/include/cv32a6_imac_sv0_config_pkg.sv

@@ -138,6 +138,7 @@ package cva6_config_pkg;
       CachedRegionAddrBase: 1024'({64'h8000_0000}),
       CachedRegionLength: 1024'({64'h40000000}),
       MaxOutstandingStores: unsigned'(7),
-      DebugEn: bit'(1)
+      DebugEn: bit'(1),
+      NonIdemPotenceEn: bit'(0)
   };
 endpackage

core/include/cv32a6_imac_sv32_config_pkg.sv

@@ -138,7 +138,8 @@ package cva6_config_pkg;
       CachedRegionAddrBase: 1024'({64'h8000_0000}),
       CachedRegionLength: 1024'({64'h40000000}),
       MaxOutstandingStores: unsigned'(7),
-      DebugEn: bit'(1)
+      DebugEn: bit'(1),
+      NonIdemPotenceEn: bit'(0)
   };
 
 endpackage

core/include/cv32a6_imafc_sv32_config_pkg.sv

@@ -138,7 +138,8 @@ package cva6_config_pkg;
       CachedRegionAddrBase: 1024'({64'h8000_0000}),
       CachedRegionLength: 1024'({64'h40000000}),
       MaxOutstandingStores: unsigned'(7),
-      DebugEn: bit'(1)
+      DebugEn: bit'(1),
+      NonIdemPotenceEn: bit'(0)
   };
 
 endpackage

core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv

@@ -137,7 +137,8 @@ package cva6_config_pkg;
       CachedRegionAddrBase: 1024'({64'h8000_0000}),
       CachedRegionLength: 1024'({64'h40000000}),
       MaxOutstandingStores: unsigned'(7),
-      DebugEn: bit'(1)
+      DebugEn: bit'(1),
+      NonIdemPotenceEn: bit'(0)
   };
 
 endpackage

core/include/cv64a6_imafdc_sv39_config_pkg.sv

@@ -138,7 +138,8 @@ package cva6_config_pkg;
       CachedRegionAddrBase: 1024'({64'h8000_0000}),
       CachedRegionLength: 1024'({64'h40000000}),
       MaxOutstandingStores: unsigned'(7),
-      DebugEn: bit'(1)
+      DebugEn: bit'(1),
+      NonIdemPotenceEn: bit'(0)
   };
 
 endpackage

core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv

@@ -144,7 +144,8 @@ package cva6_config_pkg;
       ),
       CachedRegionAddrBase: 1024'({64'h8000_0000}),
       CachedRegionLength: 1024'({64'h40000000}),
-      DebugEn: bit'(1)
+      DebugEn: bit'(1),
+      NonIdemPotenceEn: bit'(0)
   };
 
 endpackage

core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv

@@ -138,7 +138,8 @@ package cva6_config_pkg;
       CachedRegionAddrBase: 1024'({64'h8000_0000}),
       CachedRegionLength: 1024'({64'h40000000}),
       MaxOutstandingStores: unsigned'(7),
-      DebugEn: bit'(1)
+      DebugEn: bit'(1),
+      NonIdemPotenceEn: bit'(0)
   };
 
 endpackage

core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv

@@ -138,7 +138,8 @@ package cva6_config_pkg;
       CachedRegionAddrBase: 1024'({64'h8000_0000}),
       CachedRegionLength: 1024'({64'h40000000}),
       MaxOutstandingStores: unsigned'(7),
-      DebugEn: bit'(1)
+      DebugEn: bit'(1),
+      NonIdemPotenceEn: bit'(0)
   };
 
 endpackage

core/include/cv64a6_imafdcv_sv39_config_pkg.sv

@@ -137,6 +137,7 @@ package cva6_config_pkg;
       CachedRegionAddrBase: 1024'({64'h8000_0000}),
       CachedRegionLength: 1024'({64'h40000000}),
       MaxOutstandingStores: unsigned'(7),
-      DebugEn: bit'(1)
+      DebugEn: bit'(1),
+      NonIdemPotenceEn: bit'(0)
   };
 endpackage

core/load_unit.sv

@@ -189,7 +189,7 @@ module load_unit
   assign paddr_ni = config_pkg::is_inside_nonidempotent_regions(CVA6Cfg, {{52-riscv::PPNW{1'b0}}, dtlb_ppn_i, 12'd0});
   assign not_commit_time = commit_tran_id_i != lsu_ctrl_i.trans_id;
   assign inflight_stores = (!dcache_wbuffer_not_ni_i || !store_buffer_empty_i);
-  assign stall_ni = (inflight_stores || not_commit_time) && paddr_ni;
+  assign stall_ni = (inflight_stores || not_commit_time) && (paddr_ni && CVA6Cfg.NonIdemPotenceEn);
 
   // ---------------
   // Load Control
@@ -235,7 +235,7 @@ module load_unit
                   state_d  = SEND_TAG;
                   pop_ld_o = 1'b1;
                   // translation valid but this is to NC and the WB is not yet empty.
-                end else begin
+                end else if (CVA6Cfg.NonIdemPotenceEn) begin
                   state_d = ABORT_TRANSACTION_NI;
                 end
               end
@@ -258,30 +258,43 @@ module load_unit
       // abort the previous request - free the D$ arbiter
       // we are here because of a TLB miss, we need to abort the current request and give way for the
       // PTW walker to satisfy the TLB miss
-      ABORT_TRANSACTION, ABORT_TRANSACTION_NI: begin
-        req_port_o.kill_req = 1'b1;
-        req_port_o.tag_valid = 1'b1;
-        // either re-do the request or wait until the WB is empty (depending on where we came from).
-        state_d = (state_q == ABORT_TRANSACTION_NI) ? WAIT_WB_EMPTY : WAIT_TRANSLATION;
+      ABORT_TRANSACTION: begin
+        if(ariane_pkg::MMU_PRESENT) begin
+          req_port_o.kill_req = 1'b1;
+          req_port_o.tag_valid = 1'b1;
+          // wait until the WB is empty
+          state_d = WAIT_TRANSLATION;
+        end
+      end
+
+      ABORT_TRANSACTION_NI: begin
+        if(CVA6Cfg.NonIdemPotenceEn) begin
+          req_port_o.kill_req = 1'b1;
+          req_port_o.tag_valid = 1'b1;
+          // re-do the request
+          state_d = WAIT_WB_EMPTY;
+        end
       end
 
       // Wait until the write-back buffer is empty in the data cache.
       WAIT_WB_EMPTY: begin
         // the write buffer is empty, so lets go and re-do the translation.
-        if (dcache_wbuffer_not_ni_i) state_d = WAIT_TRANSLATION;
+        if (CVA6Cfg.NonIdemPotenceEn && dcache_wbuffer_not_ni_i) state_d = WAIT_TRANSLATION;
       end
 
       WAIT_TRANSLATION: begin
-        translation_req_o = 1'b1;
-        // we've got a hit and we can continue with the request process
-        if (dtlb_hit_i) state_d = WAIT_GNT;
-
-        // we got an exception
-        if (ex_i.valid) begin
-          // the next state will be the idle state
-          state_d  = IDLE;
-          // pop load - but only if we are not getting an rvalid in here - otherwise we will over-write an incoming transaction
-          pop_ld_o = ~req_port_i.data_rvalid;
+        if(ariane_pkg::MMU_PRESENT || CVA6Cfg.NonIdemPotenceEn) begin
+          translation_req_o = 1'b1;
+          // we've got a hit and we can continue with the request process
+          if (dtlb_hit_i) state_d = WAIT_GNT;
+
+          // we got an exception
+          if (ex_i.valid) begin
+            // the next state will be the idle state
+            state_d  = IDLE;
+            // pop load - but only if we are not getting an rvalid in here - otherwise we will over-write an incoming transaction
+            pop_ld_o = ~req_port_i.data_rvalid;
+          end
         end
       end
 
@@ -301,7 +314,7 @@ module load_unit
               state_d  = SEND_TAG;
               pop_ld_o = 1'b1;
               // translation valid but this is to NC and the WB is not yet empty.
-            end else begin
+            end else if (CVA6Cfg.NonIdemPotenceEn) begin
               state_d = ABORT_TRANSACTION_NI;
             end
           end
@@ -335,7 +348,7 @@ module load_unit
                   state_d  = SEND_TAG;
                   pop_ld_o = 1'b1;
                   // translation valid but this is to NC and the WB is not yet empty.
-                end else begin
+                end else if (CVA6Cfg.NonIdemPotenceEn) begin
                   state_d = ABORT_TRANSACTION_NI;
                 end
               end
@@ -406,7 +419,7 @@ module load_unit
     // exceptions can retire out-of-order -> but we need to give priority to non-excepting load and stores
     // so we simply check if we got an rvalid if so we prioritize it by not retiring the exception - we simply go for another
     // round in the load FSM
-    if ((state_q == WAIT_TRANSLATION) && !req_port_i.data_rvalid && ex_i.valid && valid_i) begin
+    if ((ariane_pkg::MMU_PRESENT || CVA6Cfg.NonIdemPotenceEn) && (state_q == WAIT_TRANSLATION) && !req_port_i.data_rvalid && ex_i.valid && valid_i) begin
       trans_id_o = lsu_ctrl_i.trans_id;
       valid_o = 1'b1;
       ex_o.valid = 1'b1;

corev_apu/fpga/src/ariane_xilinx.sv

@@ -209,7 +209,8 @@ localparam config_pkg::cva6_cfg_t CVA6Cfg = '{
   CachedRegionAddrBase:  1024'({ariane_soc::DRAMBase}),
   CachedRegionLength:    1024'({ariane_soc::DRAMLength}),
   MaxOutstandingStores:  unsigned'(7),
-  DebugEn: bit'(1)
+  DebugEn: bit'(1),
+  NonIdemPotenceEn: bit'(0)
 };
 
 localparam type rvfi_instr_t = logic;