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fix merge conflict
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fatimasaleem committed Oct 20, 2023
1 parent d4bf08b commit 41d0a2a
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2 changes: 0 additions & 2 deletions core/cache_subsystem/wt_dcache_missunit.sv
Original file line number Diff line number Diff line change
Expand Up @@ -295,8 +295,6 @@ module wt_dcache_missunit

assign amo_req_d = amo_req_i.req;

end

// outgoing memory requests (AMOs are always uncached)
assign mem_data_o.tid = (CVA6Cfg.RVA && amo_sel) ? AmoTxId : miss_id_i[miss_port_idx];
assign mem_data_o.nc = (CVA6Cfg.RVA && amo_sel) ? 1'b1 : miss_nc_i[miss_port_idx];
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