Add CSRs tests for embedded config

.gitlab-ci.yml

@@ -413,11 +413,26 @@ directed_isacov-tests:
     - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
     - python3 .gitlab-ci/scripts/report_pass.py
 
-directed_xif-tests:
+csr_embedded_tests:
   extends:
     - .verif_test
   variables:
+    DASHBOARD_JOB_TITLE: "csr_embedded test $DV_TARGET"
+    DASHBOARD_JOB_DESCRIPTION: "CSR Test generated using UVM-REG"
     DASHBOARD_SORT_INDEX: 15
+    DASHBOARD_JOB_CATEGORY: "CSR tests"
+    DV_SIMULATORS: "vcs-uvm"
+  script:
+    - mkdir -p artifacts/coverage
+    - source verif/regress/dv-csr-embedded-tests.sh
+    - mv verif/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage
+    - python3 .gitlab-ci/scripts/report_pass.py
+
+directed_xif-tests:
+  extends:
+    - .verif_test
+  variables:
+    DASHBOARD_SORT_INDEX: 16
     DASHBOARD_JOB_CATEGORY: "Functional Coverage"
   parallel:
     matrix:
@@ -496,6 +511,7 @@ code_coverage-report:
     - directed_isacov-tests
     - generated_xif_tests
     - directed_xif-tests
+    - csr_embedded_tests
   variables:
     DASHBOARD_JOB_TITLE: "Report merge coverage"
     DASHBOARD_JOB_DESCRIPTION: "Report merge coverage of generated tests"

verif/regress/dv-csr-embedded-tests.sh

@@ -0,0 +1,33 @@
+# Copyright 2023 Thales DIS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Ayoub JALALI - Thales
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+  echo "Error: RISCV variable undefined"
+  return
+fi
+
+# install the required tools
+source verif/regress/install-cva6.sh
+source verif/regress/install-riscv-dv.sh
+
+export cov=1 #enable the Code Coverage
+
+if ! [ -n "$DV_TARGET" ]; then
+  DV_TARGET=cv32a6_embedded
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+  DV_SIMULATORS=vcs-uvm,spike
+fi
+
+cd verif/sim/
+python3 cva6.py --testlist=../tests/testlist_csr_embedded.yaml --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
+
+cd -

verif/tests/custom/csr_embedded/csr_test.S

@@ -0,0 +1,42 @@
+# Copyright 2023 Thales DIS France SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+
+#include "csrrst_test.S"
+#include "csrrw_fields_test.S"
+#include "csrrw_test.S"
+#include "csrrwi_test.S"
+#include "csrcs_test.S"
+#include "csrcsi_test.S"
+
+.globl main
+main:
+    #Start CSR tests: all tests
+    call csrrst
+    call csrrw_fields
+    call csrrw
+    call csrrwi
+    call csrcs
+    call csrcsi
+
+    #End of csr test
+    j csr_pass
+
+csr_pass:
+    li x1, 0
+    slli x1, x1, 1
+    addi x1, x1, 1
+    sw x1, tohost, x30
+    self_loop: j self_loop
+
+csr_fail:
+    li x1, 1
+    slli x1, x1, 1
+    addi x1, x1, 1
+    sw x1, tohost, x30
+    self_loop_2: j self_loop_2
+