added the condition for updating the tlb only after a miss is incurred

openhwgroup · Feb 6, 2024 · 3104fb7 · 3104fb7
1 parent 42b21b8
commit 3104fb7
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/core/mmu_sv32/cva6_tlb_sv32.sv b/core/mmu_sv32/cva6_tlb_sv32.sv
@@ -124,7 +124,7 @@ module cva6_tlb_sv32
         else if ((!content_q[i].g) && (vaddr_to_be_flushed_is0) && (asid_to_be_flushed_i == tags_q[i].asid[ASID_WIDTH-1:0]) && (!asid_to_be_flushed_is0))
           tags_n[i].valid = 1'b0;
         // normal replacement
-      end else if (update_i.valid & replace_en[i]) begin
+      end else if (update_i.valid & replace_en[i] & !lu_hit_o) begin
         // update tag array
         tags_n[i] = '{
             asid: update_i.asid,