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add csr in rvfi
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@yanicasa
yanicasa committed Feb 16, 2024
1 parent 6e8e265 commit 2e144c1
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Showing 11 changed files with 550 additions and 59 deletions.
335 changes: 317 additions & 18 deletions core/csr_regfile.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,7 @@ module csr_regfile
import ariane_pkg::*;
#(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter bit IsRVFI = bit'(cva6_config_pkg::CVA6ConfigRvfiTrace),
parameter int AsidWidth = 1,
parameter int unsigned MHPMCounterNum = 6
) (
Expand Down Expand Up @@ -135,8 +136,11 @@ module csr_regfile
// PMP addresses - ACC_DISPATCHER
output logic [ 15:0][riscv::PLEN-3:0] pmpaddr_o,
// TO_BE_COMPLETED - PERF_COUNTERS
output logic [ 31:0] mcountinhibit_o
output logic [ 31:0] mcountinhibit_o,
// RVFI
rvfi_csr_t rvfi_csr_o
);

// internal signal to keep track of access exceptions
logic read_access_exception, update_access_exception, privilege_violation;
logic csr_we, csr_read;
Expand Down Expand Up @@ -191,8 +195,8 @@ module csr_regfile
logic [63:0] cycle_q, cycle_d;
logic [63:0] instret_q, instret_d;

riscv::pmpcfg_t [15:0] pmpcfg_q, pmpcfg_d;
logic [15:0][riscv::PLEN-3:0] pmpaddr_q, pmpaddr_d;
riscv::pmpcfg_t [15:0] pmpcfg_q, pmpcfg_d, pmpcfg_next;
logic [15:0][riscv::PLEN-3:0] pmpaddr_q, pmpaddr_d, pmpaddr_next;
logic [MHPMCounterNum+3-1:0] mcountinhibit_d, mcountinhibit_q;
logic [3:0] index;

Expand Down Expand Up @@ -1663,23 +1667,29 @@ module csr_regfile
// wait for interrupt
wfi_q <= wfi_d;
// pmp
for (int i = 0; i < 16; i++) begin
if (i < CVA6Cfg.NrPMPEntries) begin
// We only support >=8-byte granularity, NA4 is disabled
if(!CVA6Cfg.PMPEntryReadOnly[i] && pmpcfg_d[i].addr_mode != riscv::NA4 && !(pmpcfg_d[i].access_type.r == '0 && pmpcfg_d[i].access_type.w == '1)) begin
pmpcfg_q[i] <= pmpcfg_d[i];
end else begin
pmpcfg_q[i] <= pmpcfg_q[i];
end
if (!CVA6Cfg.PMPEntryReadOnly[i]) begin
pmpaddr_q[i] <= pmpaddr_d[i];
end else begin
pmpaddr_q[i] <= pmpaddr_q[i];
end
pmpcfg_q <= pmpcfg_next;
pmpaddr_q <= pmpaddr_next;
end
end

// write logic pmp
always_comb begin : write
for (int i = 0; i < 16; i++) begin
if (i < CVA6Cfg.NrPMPEntries) begin
// We only support >=8-byte granularity, NA4 is disabled
if(!CVA6Cfg.PMPEntryReadOnly[i] && pmpcfg_d[i].addr_mode != riscv::NA4 && !(pmpcfg_d[i].access_type.r == '0 && pmpcfg_d[i].access_type.w == '1)) begin
pmpcfg_next[i] <= pmpcfg_d[i];
end else begin
pmpcfg_q[i] <= '0;
pmpaddr_q[i] <= '0;
pmpcfg_next[i] <= pmpcfg_q[i];
end
if (!CVA6Cfg.PMPEntryReadOnly[i]) begin
pmpaddr_next[i] <= pmpaddr_d[i];
end else begin
pmpaddr_next[i] <= pmpaddr_q[i];
end
end else begin
pmpcfg_next[i] <= '0;
pmpaddr_next[i] <= '0;
end
end
end
Expand All @@ -1695,4 +1705,293 @@ module csr_regfile
$stop();
end
//pragma translate_on

//pragma translate_off

if (IsRVFI) begin

//-------------
// RVFI
//-------------
assign rvfi_csr_o.fflags = CVA6Cfg.FpPresent ?
'{rdata: {'0, fcsr_q.fflags}, wdata: {'0, fcsr_d.fflags}, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.frm = CVA6Cfg.FpPresent ?
'{rdata: {'0, fcsr_q.frm}, wdata: {'0, fcsr_d.frm}, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.fcsr = CVA6Cfg.FpPresent ?
'{
rdata: {'0, fcsr_q.frm, fcsr_q.fflags},
wdata: {'0, fcsr_d.frm, fcsr_d.fflags},
rmask: '1,
wmask: '1
}
: '0;
assign rvfi_csr_o.ftran = CVA6Cfg.FpPresent ?
'{rdata: {'0, fcsr_q.fprec}, wdata: {'0, fcsr_d.fprec}, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.dcsr = CVA6Cfg.DebugEn ?
'{rdata: {'0, dcsr_q}, wdata: {'0, dcsr_d}, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.dpc = CVA6Cfg.DebugEn ?
'{rdata: {dpc_q}, wdata: dpc_d, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.dscratch0 = CVA6Cfg.DebugEn ?
'{rdata: dscratch0_q, wdata: dscratch0_d, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.dscratch1 = CVA6Cfg.DebugEn ?
'{rdata: dscratch1_q, wdata: dscratch1_d, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.sstatus = CVA6Cfg.RVS ?
'{
rdata: mstatus_extended & ariane_pkg::SMODE_STATUS_READ_MASK[riscv::XLEN-1:0],
wdata: mstatus_extended & ariane_pkg::SMODE_STATUS_READ_MASK[riscv::XLEN-1:0],
rmask: '1,
wmask: '1
}
: '0;
assign rvfi_csr_o.sie = CVA6Cfg.RVS ?
'{rdata: mie_q & mideleg_q, wdata: mie_d & mideleg_d, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.sip = CVA6Cfg.RVS ?
'{rdata: mip_q & mideleg_q, wdata: mip_d & mideleg_d, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.stvec = CVA6Cfg.RVS ?
'{rdata: stvec_q, wdata: stvec_d, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.scounteren = CVA6Cfg.RVS ?
'{rdata: scounteren_q, wdata: scounteren_d, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.sscratch = CVA6Cfg.RVS ?
'{rdata: sscratch_q, wdata: sscratch_d, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.sepc = CVA6Cfg.RVS ?
'{rdata: sepc_q, wdata: sepc_d, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.scause = CVA6Cfg.RVS ?
'{rdata: scause_q, wdata: scause_d, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.stval = CVA6Cfg.RVS ?
'{rdata: stval_q, wdata: stval_d, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.satp = CVA6Cfg.RVS ?
'{rdata: satp_q, wdata: satp_d, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.mstatus = '{
rdata: mstatus_extended,
wdata: mstatus_extended,
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.mstatush = riscv::XLEN == 32 ?
'{rdata: '0, wdata: '0, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.misa = '{rdata: IsaCode, wdata: IsaCode, rmask: '1, wmask: '1};
assign rvfi_csr_o.medeleg = CVA6Cfg.RVS ?
'{rdata: medeleg_q, wdata: medeleg_d, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.mideleg = CVA6Cfg.RVS ?
'{rdata: mideleg_q, wdata: mideleg_d, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.mie = '{rdata: mie_q, wdata: mie_d, rmask: '1, wmask: '1};
assign rvfi_csr_o.mtvec = '{rdata: mtvec_q, wdata: mtvec_d, rmask: '1, wmask: '1};
assign rvfi_csr_o.mcounteren = '{
rdata: mcounteren_q,
wdata: mcounteren_d,
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.mscratch = '{rdata: mscratch_q, wdata: mscratch_d, rmask: '1, wmask: '1};
assign rvfi_csr_o.mepc = '{rdata: mepc_q, wdata: mepc_d, rmask: '1, wmask: '1};
assign rvfi_csr_o.mcause = '{rdata: mcause_q, wdata: mcause_d, rmask: '1, wmask: '1};
assign rvfi_csr_o.mtval = '{rdata: mtval_q, wdata: mtval_d, rmask: '1, wmask: '1};
assign rvfi_csr_o.mip = '{rdata: mip_q, wdata: mip_d, rmask: '1, wmask: '1};
assign rvfi_csr_o.menvcfg = '{
rdata: {'0, fiom_q},
wdata: {'0, fiom_d},
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.menvcfgh = riscv::XLEN == 32 ?
'{rdata: '0, wdata: '0, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.mvendorid = '{
rdata: OPENHWGROUP_MVENDORID,
wdata: OPENHWGROUP_MVENDORID,
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.marchid = '{
rdata: ARIANE_MARCHID,
wdata: ARIANE_MARCHID,
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.mhartid = '{rdata: hart_id_i, wdata: hart_id_i, rmask: '1, wmask: '1};
assign rvfi_csr_o.mcountinhibit = '{
rdata: {'0, mcountinhibit_q},
wdata: {'0, mcountinhibit_d},
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.mcycle = '{
rdata: cycle_q[riscv::XLEN-1:0],
wdata: cycle_d[riscv::XLEN-1:0],
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.mcycleh = riscv::XLEN == 32 ?
'{rdata: cycle_q[63:32], wdata: cycle_d[63:32], rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.minstret = '{
rdata: instret_q[riscv::XLEN-1:0],
wdata: instret_d[riscv::XLEN-1:0],
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.minstreth = riscv::XLEN == 32 ?
'{rdata: instret_q[63:32], wdata: instret_d[63:32], rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.cycle = '{
rdata: cycle_q[riscv::XLEN-1:0],
wdata: cycle_d[riscv::XLEN-1:0],
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.cycleh = riscv::XLEN == 32 ?
'{rdata: cycle_q[63:32], wdata: cycle_d[63:32], rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.instret = '{
rdata: instret_q[riscv::XLEN-1:0],
wdata: instret_d[riscv::XLEN-1:0],
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.instreth = riscv::XLEN == 32 ?
'{rdata: instret_q[63:32], wdata: instret_d[63:32], rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.dcache = '{rdata: dcache_q, wdata: dcache_d, rmask: '1, wmask: '1};
assign rvfi_csr_o.icache = '{rdata: icache_q, wdata: icache_d, rmask: '1, wmask: '1};
assign rvfi_csr_o.acc_cons = CVA6Cfg.EnableAccelerator ?
'{rdata: acc_cons_q, wdata: acc_cons_d, rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.pmpcfg0 = '{
rdata: pmpcfg_q[riscv::XLEN/8-1:0],
wdata: pmpcfg_d[riscv::XLEN/8-1:0],
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.pmpcfg1 = riscv::XLEN == 32 ?
'{rdata: pmpcfg_q[7:4], wdata: pmpcfg_d[7:4], rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.pmpcfg2 = '{
rdata: pmpcfg_q[8+:riscv::XLEN/8],
wdata: pmpcfg_d[8+:riscv::XLEN/8],
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.pmpcfg3 = riscv::XLEN == 32 ?
'{rdata: pmpcfg_q[15:12], wdata: pmpcfg_d[15:12], rmask: '1, wmask: '1}
: '0;
assign rvfi_csr_o.pmpaddr0 = '{
rdata: {'0, pmpaddr_q[0][riscv::PLEN-3:0]},
wdata: {'0, pmpaddr_d[0][riscv::PLEN-3:0]},
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.pmpaddr1 = '{
rdata: {'0, pmpaddr_q[1][riscv::PLEN-3:0]},
wdata: {'0, pmpaddr_d[1][riscv::PLEN-3:0]},
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.pmpaddr2 = '{
rdata: {'0, pmpaddr_q[2][riscv::PLEN-3:0]},
wdata: {'0, pmpaddr_d[2][riscv::PLEN-3:0]},
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.pmpaddr3 = '{
rdata: {'0, pmpaddr_q[3][riscv::PLEN-3:0]},
wdata: {'0, pmpaddr_d[3][riscv::PLEN-3:0]},
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.pmpaddr4 = '{
rdata: {'0, pmpaddr_q[4][riscv::PLEN-3:0]},
wdata: {'0, pmpaddr_d[4][riscv::PLEN-3:0]},
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.pmpaddr5 = '{
rdata: {'0, pmpaddr_q[5][riscv::PLEN-3:0]},
wdata: {'0, pmpaddr_d[5][riscv::PLEN-3:0]},
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.pmpaddr6 = '{
rdata: {'0, pmpaddr_q[6][riscv::PLEN-3:0]},
wdata: {'0, pmpaddr_d[6][riscv::PLEN-3:0]},
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.pmpaddr7 = '{
rdata: {'0, pmpaddr_q[7][riscv::PLEN-3:0]},
wdata: {'0, pmpaddr_d[7][riscv::PLEN-3:0]},
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.pmpaddr8 = '{
rdata: {'0, pmpaddr_q[8][riscv::PLEN-3:0]},
wdata: {'0, pmpaddr_d[8][riscv::PLEN-3:0]},
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.pmpaddr9 = '{
rdata: {'0, pmpaddr_q[9][riscv::PLEN-3:0]},
wdata: {'0, pmpaddr_d[9][riscv::PLEN-3:0]},
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.pmpaddr10 = '{
rdata: {'0, pmpaddr_q[10][riscv::PLEN-3:0]},
wdata: {'0, pmpaddr_d[10][riscv::PLEN-3:0]},
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.pmpaddr11 = '{
rdata: {'0, pmpaddr_q[11][riscv::PLEN-3:0]},
wdata: {'0, pmpaddr_d[11][riscv::PLEN-3:0]},
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.pmpaddr12 = '{
rdata: {'0, pmpaddr_q[12][riscv::PLEN-3:0]},
wdata: {'0, pmpaddr_d[12][riscv::PLEN-3:0]},
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.pmpaddr13 = '{
rdata: {'0, pmpaddr_q[13][riscv::PLEN-3:0]},
wdata: {'0, pmpaddr_d[13][riscv::PLEN-3:0]},
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.pmpaddr14 = '{
rdata: {'0, pmpaddr_q[14][riscv::PLEN-3:0]},
wdata: {'0, pmpaddr_d[14][riscv::PLEN-3:0]},
rmask: '1,
wmask: '1
};
assign rvfi_csr_o.pmpaddr15 = '{
rdata: {'0, pmpaddr_q[15][riscv::PLEN-3:0]},
wdata: {'0, pmpaddr_d[15][riscv::PLEN-3:0]},
rmask: '1,
wmask: '1
};

end //is RVFI

//pragma translate_on

endmodule
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