make cv32a65x superscalar (#2348)

openhwgroup · Jul 10, 2024 · 2dcb741 · 2dcb741
1 parent 214444c
commit 2dcb741
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Showing 3 changed files with 4 additions and 4 deletions.
diff --git a/.gitlab-ci/expected_synth.yml b/.gitlab-ci/expected_synth.yml
@@ -1,2 +1,2 @@
 cv32a65x:
-  gates: 129171
+  gates: 162333
diff --git a/.gitlab-ci/scripts/report_benchmark.py b/.gitlab-ci/scripts/report_benchmark.py
@@ -18,7 +18,7 @@
 # Will fail if the number of cycles is different from this one
 valid_cycles = {
     'dhrystone': 217900,
-    'coremark': 686072,
+    'coremark': 549055,
 }
 
 for arg in sys.argv[1:]:

diff --git a/core/include/cv32a65x_config_pkg.sv b/core/include/cv32a65x_config_pkg.sv
@@ -18,13 +18,13 @@ package cva6_config_pkg;
   localparam CVA6ConfigAxiDataWidth = 64;  // axi_pkg.sv
   localparam CVA6ConfigDataUserWidth = 32;  // axi_pkg.sv
 
-  localparam CVA6ConfigNrScoreboardEntries = 4;  // cvxif_pkg.sv
+  localparam CVA6ConfigNrScoreboardEntries = 8;  // cvxif_pkg.sv
 
   localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
       XLEN: unsigned'(CVA6ConfigXlen),
       FpgaEn: bit'(0),
       TechnoCut: bit'(1),
-      SuperscalarEn: bit'(0),
+      SuperscalarEn: bit'(1),
       NrCommitPorts: unsigned'(1),
       AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
       AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),