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Fix branch misalignement condition
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Related to #1300
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JeanRochCoulon authored Dec 10, 2023
1 parent a837e94 commit 2985909
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion core/branch_unit.sv
Original file line number Diff line number Diff line change
Expand Up @@ -99,6 +99,6 @@ module branch_unit #(
branch_exception_o.tval = {{riscv::XLEN - riscv::VLEN{pc_i[riscv::VLEN-1]}}, pc_i};
// Only throw instruction address misaligned exception if this is indeed a `taken` conditional branch or
// an unconditional jump
if (branch_valid_i && target_address[0] != 1'b0 && jump_taken) branch_exception_o.valid = 1'b1;
if (branch_valid_i && (target_address[1:0] != 2'b00) && jump_taken) branch_exception_o.valid = 1'b1;
end
endmodule

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