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[CI] use spike tandem on smoke-tests (#2438)
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valentinThomazic authored Aug 22, 2024
1 parent 76e5b40 commit 28affa2
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28 changes: 17 additions & 11 deletions .gitlab-ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -131,9 +131,9 @@ build_tools:
- echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC

.simu_after_script: &simu_after_script
- for i in $(find verif/sim/out*/[vq]*_sim -type f \( -name "*.csv" -o -name "*.iss" \)) ; do head -10000 $i > artifacts/logs/$(basename $i).head ; done
- for i in $(find verif/sim/out*/[vq]*_sim -type f \( -name "*.csv" -o -name "*.iss" -o name "*.yaml" \)) ; do head -10000 $i > artifacts/logs/$(basename $i).head ; done
- head -10000 verif/sim/logfile.log > artifacts/logs/logfile.log.head
- python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log
- if [ -n "$SPIKE_TANDEM" ]; then python3 .gitlab-ci/scripts/report_tandem.py verif/sim/out*/"$DV_SIMULATORS"_sim; else python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log; fi

smoke:
extends:
Expand All @@ -149,12 +149,13 @@ smoke:
matrix:
- DV_SIMULATORS:
- "veri-testharness,spike"
- "vcs-testharness,spike"
- "vcs-testharness"
- "questa-testharness,spike"
- "vcs-uvm,spike"
- "vcs-uvm"
script:
- source $QUESTA_BASHRC
- bash verif/regress/smoke-tests.sh
- if [[ $DV_SIMULATORS == *"spike"* ]]; then unset SPIKE_TANDEM; fi # dirty hack to do trace comparison between tandem execution and spike standalone
- !reference [.simu_after_script]

gen_smoke:
Expand All @@ -165,9 +166,9 @@ gen_smoke:
DASHBOARD_JOB_DESCRIPTION: "Short generated tests to challenge the CVA6-DV on STEP1 configuration"
DASHBOARD_SORT_INDEX: 0
DASHBOARD_JOB_CATEGORY: "Basic"
DV_SIMULATORS: "vcs-uvm,spike"
SPIKE_TANDEM: 1
DV_SIMULATORS: "vcs-uvm"
COLLECT_SIMU_LOGS: 1
SPIKE_TANDEM: 1
script:
- bash verif/regress/smoke-gen_tests.sh
- !reference [.simu_after_script]
Expand Down Expand Up @@ -326,7 +327,8 @@ riscv_arch_test:
DASHBOARD_JOB_DESCRIPTION: "Compliance regression suite"
DASHBOARD_SORT_INDEX: 0
DASHBOARD_JOB_CATEGORY: "Test suites"
DV_SIMULATORS: "veri-testharness,spike"
DV_SIMULATORS: "vcs-testharness"
SPIKE_TANDEM: 1
script: source verif/regress/dv-riscv-arch-test.sh
after_script: *simu_after_script

Expand All @@ -338,7 +340,8 @@ compliance:
DASHBOARD_JOB_DESCRIPTION: "Compliance regression suite"
DASHBOARD_SORT_INDEX: 2
DASHBOARD_JOB_CATEGORY: "Test suites"
DV_SIMULATORS: "veri-testharness,spike"
DV_SIMULATORS: "vcs-testharness"
SPIKE_TANDEM: 1
script: source verif/regress/dv-riscv-compliance.sh
after_script: *simu_after_script

Expand All @@ -350,9 +353,10 @@ riscv-tests-v:
DASHBOARD_JOB_DESCRIPTION: "Riscv-test regression suite (virtual)"
DASHBOARD_SORT_INDEX: 3
DASHBOARD_JOB_CATEGORY: "Test suites"
DV_SIMULATORS: "veri-testharness,spike"
DV_SIMULATORS: "vcs-testharness"
DV_TARGET: cv64a6_imafdc_sv39
DV_TESTLISTS: "../tests/testlist_riscv-tests-$DV_TARGET-v.yaml"
SPIKE_TANDEM: 1
script: source verif/regress/dv-riscv-tests.sh
after_script: *simu_after_script

Expand All @@ -364,8 +368,9 @@ riscv-tests-p:
DASHBOARD_JOB_DESCRIPTION: "Riscv-test regression suite (physical)"
DASHBOARD_SORT_INDEX: 4
DASHBOARD_JOB_CATEGORY: "Test suites"
DV_SIMULATORS: "veri-testharness,spike"
DV_SIMULATORS: "vcs-testharness"
DV_TESTLISTS: "../tests/testlist_riscv-tests-$DV_TARGET-p.yaml"
SPIKE_TANDEM: 1
script: source verif/regress/dv-riscv-tests.sh
after_script: *simu_after_script

Expand All @@ -387,8 +392,9 @@ mmu_sv32_tests:
DASHBOARD_JOB_DESCRIPTION: "MMU SV32 regression suite"
DASHBOARD_SORT_INDEX: 0
DASHBOARD_JOB_CATEGORY: "Test suites"
DV_SIMULATORS: "veri-testharness,spike"
DV_SIMULATORS: "vcs-testharness"
DV_TARGET: cv32a6_imac_sv32
SPIKE_TANDEM: 1
script: source verif/regress/dv-riscv-mmu-sv32-test.sh
after_script: *simu_after_script

Expand Down
97 changes: 97 additions & 0 deletions .gitlab-ci/scripts/report_tandem.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,97 @@
# Copyright 2024 Thales DIS France SAS
#
# Licensed under the Solderpad Hardware Licence, Version 0.51 (the "License");
# you may not use this file except in compliance with the License.
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
# You may obtain a copy of the License at https://solderpad.org/licenses/
#
# Original Author: Valentin Thomazic ([email protected])

import sys
import report_builder
import os
import glob
import yaml


def main():
with_logs = os.environ.get("COLLECT_SIMU_LOGS") != None
metrics_table = report_builder.TableStatusMetric('')

check_provided_args()
add_table_legend(metrics_table, with_logs)
passed_tests_count, total_tests_count = fill_table(sys.argv[1], metrics_table, with_logs)

if not report(metrics_table, passed_tests_count, total_tests_count):
sys.exit(1)


def check_provided_args():
if sys.argv[1] is None or not isinstance(sys.argv[1], str):
print("Usage : python report_tandem.py path/to/log/dir", file=sys.stderr)
sys.exit("No log directory provided !")


def add_table_legend(metrics_table, with_logs):
metrics_table.add_column("TARGET", "text")
metrics_table.add_column("ISA", "text")
metrics_table.add_column("TEST", "text")
metrics_table.add_column("TEST LIST", "text")
metrics_table.add_column("SIMULATOR", "text")
metrics_table.add_column("MISMATCHES", "text")

if with_logs:
metrics_table.add_column("OUTPUT", "log")
metrics_table.add_column("TB LOGS", "log")
metrics_table.add_column("DISASSEMBLY", "log")


def fill_table(reports_dir, metrics_table, with_logs):
simulation_reports = glob.iglob(reports_dir + "/*.yaml")
test_passed = 0
test_count = 0

for report in simulation_reports:
test_passed += add_test_row(report, metrics_table, with_logs)
test_count += 1
if test_passed != test_count:
metrics_table.fail()
return test_passed, test_count


def add_test_row(report_file, metrics_table, with_logs):
with open(report_file) as f:
report = yaml.safe_load(f)
mismatches_count = str(report["mismatches_count"]) if "mismatches_count" in report else "Not found"

row = [report["target"], report["isa"], report["test"], report["testlist"], report["simulator"], mismatches_count]

if with_logs:
logs_path = "logs/" + os.environ.get("CI_JOB_ID") + "/artifacts/logs/"
output_log = logs_path + "logfile.log.head"
log_prefix = logs_path + report['test'] + "_" + str(report["iteration"]) + "." + report["target"] \
if "iteration" in report else logs_path + report['test'] + "." + report["target"]
tb_log = log_prefix + '.log.iss.head'
disassembly = log_prefix + '.log.csv.head'

row.append(output_log)
row.append(tb_log)
row.append(disassembly)

if report["exit_cause"] == "SUCCESS" and report["exit_code"] == 0:
metrics_table.add_pass(*row)
return 1

metrics_table.add_fail(*row)
return 0


def report(metrics_table, passed_test_count, total_test_count):
report = report_builder.Report(f'{passed_test_count}/{total_test_count}')
report.add_metric(metrics_table)
report.dump("bjr")
return not report.failed


if __name__ == "__main__":
main()
4 changes: 2 additions & 2 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -271,12 +271,12 @@ incdir := $(CVA6_REPO_DIR)/vendor/pulp-platform/common_cells/include/ $(CVA6_REP
$(SPIKE_INSTALL_DIR)/include/disasm/

# Compile and sim flags
compile_flag += -incr -64 -nologo -quiet -suppress 13262 -suppress 8607 -permissive -svinputport=compat +define+$(defines) -suppress 8386 -suppress vlog-2577
compile_flag += -incr -64 -nologo -quiet -suppress 13262 -suppress 8607 +permissive -svinputport=compat +define+$(defines) -suppress 8386 -suppress vlog-2577
vopt_flag += -suppress 2085 -suppress 7063 -suppress 2698 -suppress 13262

uvm-flags += +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
questa-flags += -t 1ns -64 $(gui-sim) $(QUESTASIM_FLAGS) \
+tohost_addr=$(hell ${RISCV}/bin/${CV_SW_PREFIX}nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \
+tohost_addr=$(shell ${RISCV}/bin/${CV_SW_PREFIX}nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \
+core_name=$(target) +define+QUESTA -suppress 3356 -suppress 3579
compile_flag_vhd += -64 -nologo -quiet -2008

Expand Down
2 changes: 2 additions & 0 deletions README.md
Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
![Build Status](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml/badge.svg?branch=master)


[CVA6 dashboard](util/toolchain-builder/README.md#Prerequisites)

# CVA6 RISC-V CPU

CVA6 is a 6-stage, single-issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M, A and C extensions as specified in Volume I: User-Level ISA V 2.3 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore, it is compliant to the draft external debug spec 0.13.
Expand Down
47 changes: 26 additions & 21 deletions verif/regress/smoke-tests.sh
Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ if ! [ -n "$DV_SIMULATORS" ]; then
fi

if ! [ -n "$UVM_VERBOSITY" ]; then
export UVM_VERBOSITY=UVM_LOW
export UVM_VERBOSITY=UVM_NONE
fi

export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
Expand All @@ -42,20 +42,29 @@ CC_OPTS="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g


cd verif/sim/
make -C ../.. clean
make clean_all
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml --test rv64ui-v-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml --test rv64i_m-add-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
python3 cva6.py --testlist=../tests/testlist_custom.yaml --test custom_test_template --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --gcc_opts="$CC_OPTS -T ../tests/custom/common/test.ld" $DV_OPTS
make -C ../.. clean
make clean_all
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-add --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS --linker=../tests/custom/common/test.ld --gcc_opts="$CC_OPTS" $DV_OPTS

if [[ "$DV_SIMULATORS" != *"uvm"* ]]; then
make -C ../.. clean
make clean_all
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml --test rv64ui-v-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-add --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml --test rv64i_m-add-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
python3 cva6.py --testlist=../tests/testlist_custom.yaml --test custom_test_template --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS --gcc_opts="$CC_OPTS -T ../tests/custom/common/test.ld" $DV_OPTS
make -C ../.. clean
make clean_all
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-add --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a6_imac_sv32 --iss=$DV_SIMULATORS --linker=../tests/custom/common/test.ld --gcc_opts="$CC_OPTS" $DV_OPTS
make -C ../.. clean
make clean_all
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_mmu --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-add --iss_yaml cva6.yaml --target cv64a6_mmu --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml --test rv64i_m-add-01 --iss_yaml cva6.yaml --target cv64a6_mmu --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv64a6_mmu --iss=$DV_SIMULATORS --linker=../tests/custom/common/test.ld --gcc_opts="$CC_OPTS" $DV_OPTS
fi
make -C ../.. clean
make clean_all
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS $DV_OPTS
Expand All @@ -64,11 +73,7 @@ python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --tes
python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS --linker=../tests/custom/common/test.ld --gcc_opts="$CC_OPTS" $DV_OPTS
make -C ../.. clean
make clean_all
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_mmu --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml --test rv64ui-p-add --iss_yaml cva6.yaml --target cv64a6_mmu --iss=$DV_SIMULATORS $DV_OPTS
python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml --test rv64i_m-add-01 --iss_yaml cva6.yaml --target cv64a6_mmu --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv64a6_mmu --iss=$DV_SIMULATORS --linker=../tests/custom/common/test.ld --gcc_opts="$CC_OPTS" $DV_OPTS
make -C ../.. clean
make clean_all



cd -
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