Fix $fatal system task incorrect usage (#2619)

To fix #2618
openhwgroup · Nov 20, 2024 · 25f2f31 · 25f2f31
1 parent 7ee22cd
commit 25f2f31
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Showing 3 changed files with 6 additions and 6 deletions.
diff --git a/core/cache_subsystem/axi_adapter.sv b/core/cache_subsystem/axi_adapter.sv
@@ -201,7 +201,7 @@ module axi_adapter #(
               end else begin
                 // bursts of AMOs unsupported
                 assert (amo_i == ariane_pkg::AMO_NONE)
-                else $fatal("Bursts of atomic operations are not supported");
+                else $fatal(1, "Bursts of atomic operations are not supported");
 
                 axi_req_o.aw.len = BURST_SIZE[7:0];  // number of bursts to do
                 axi_req_o.w.data = wdata_i[0];
@@ -232,7 +232,7 @@ module axi_adapter #(
               gnt_o = axi_resp_i.ar_ready;
               if (type_i != ariane_pkg::SINGLE_REQ) begin
                 assert (amo_i == ariane_pkg::AMO_NONE)
-                else $fatal("Bursts of atomic operations are not supported");
+                else $fatal(1, "Bursts of atomic operations are not supported");
 
                 axi_req_o.ar.len = BURST_SIZE[7:0];
                 cnt_d = BURST_SIZE[ADDR_INDEX-1:0];

diff --git a/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv b/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv
@@ -407,13 +407,13 @@ module cva6_hpdcache_subsystem_axi_arbiter
   //  pragma translate_off
   initial
     assert (CVA6Cfg.MEM_TID_WIDTH <= AxiIdWidth)
-    else $fatal("MEM_TID_WIDTH shall be less or equal to AxiIdWidth");
+    else $fatal(1, "MEM_TID_WIDTH shall be less or equal to AxiIdWidth");
   initial
     assert (CVA6Cfg.AxiDataWidth <= CVA6Cfg.ICACHE_LINE_WIDTH)
-    else $fatal("AxiDataWidth shall be less or equal to the width of a Icache line");
+    else $fatal(1, "AxiDataWidth shall be less or equal to the width of a Icache line");
   initial
     assert (CVA6Cfg.AxiDataWidth <= CVA6Cfg.DCACHE_LINE_WIDTH)
-    else $fatal("AxiDataWidth shall be less or equal to the width of a Dcache line");
+    else $fatal(1, "AxiDataWidth shall be less or equal to the width of a Dcache line");
   //  pragma translate_on
   //  }}}
 

diff --git a/corev_apu/tb/tb_cva6_icache/hdl/tlb_emul.sv b/corev_apu/tb/tb_cva6_icache/hdl/tlb_emul.sv
@@ -36,7 +36,7 @@ always_ff @(posedge clk_i or negedge rst_ni) begin : p_tlb_rand
   automatic int rnd = 0;
 
   assert(TlbRandHitRate<=100 && TlbRandHitRate>=0) else
-    $fatal("TlbRandHitRate must be a percentage");
+    $fatal(1, "TlbRandHitRate must be a percentage");
 
   if(~rst_ni) begin
     tlb_ready_q <= '0;