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Separate RAW and WAW process to fix CVXIF with Superscalar (#2395)
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Gchauvon authored Jul 26, 2024
1 parent 96b0508 commit 211af02
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Showing 7 changed files with 194 additions and 177 deletions.
13 changes: 6 additions & 7 deletions core/cvxif_example/compressed_instr_decoder.sv
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Expand Up @@ -7,13 +7,12 @@
//
// Original Author: Guillaume Chauvon

module compressed_instr_decoder
import cvxif_instr_pkg::*;
#(
parameter int NbInstr = 1,
parameter copro_compressed_resp_t CoproInstr [NbInstr] = {0},
parameter type x_compressed_req_t = logic,
parameter type x_compressed_resp_t = logic
module compressed_instr_decoder #(
parameter type copro_compressed_resp_t = logic,
parameter int NbInstr = 1,
parameter copro_compressed_resp_t CoproInstr [NbInstr] = {0},
parameter type x_compressed_req_t = logic,
parameter type x_compressed_resp_t = logic
) (
input logic clk_i,
input logic rst_ni,
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3 changes: 3 additions & 0 deletions core/cvxif_example/cvxif_example_coprocessor.sv
Original file line number Diff line number Diff line change
Expand Up @@ -71,6 +71,7 @@ module cvxif_example_coprocessor
assign register_valid = cvxif_req_i.register_valid;

compressed_instr_decoder #(
.copro_compressed_resp_t(cvxif_instr_pkg::copro_compressed_resp_t),
.NbInstr(cvxif_instr_pkg::NbCompInstr),
.CoproInstr(cvxif_instr_pkg::CoproCompInstr),
.x_compressed_req_t(x_compressed_req_t),
Expand All @@ -85,6 +86,8 @@ module cvxif_example_coprocessor
);

instr_decoder #(
.copro_issue_resp_t (cvxif_instr_pkg::copro_issue_resp_t),
.opcode_t (cvxif_instr_pkg::opcode_t),
.NbInstr (cvxif_instr_pkg::NbInstr),
.CoproInstr(cvxif_instr_pkg::CoproInstr),
.NrRgprPorts(NrRgprPorts),
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26 changes: 13 additions & 13 deletions core/cvxif_example/instr_decoder.sv
Original file line number Diff line number Diff line change
Expand Up @@ -7,18 +7,18 @@
//
// Original Author: Guillaume Chauvon

module instr_decoder
import cvxif_instr_pkg::*;
#(
parameter int NbInstr = 1,
parameter copro_issue_resp_t CoproInstr [NbInstr] = {0},
parameter int unsigned NrRgprPorts = 2,
parameter type hartid_t = logic,
parameter type id_t = logic,
parameter type x_issue_req_t = logic,
parameter type x_issue_resp_t = logic,
parameter type x_register_t = logic,
parameter type registers_t = logic
module instr_decoder #(
parameter type copro_issue_resp_t = logic,
parameter type opcode_t = logic,
parameter int NbInstr = 1,
parameter copro_issue_resp_t CoproInstr [NbInstr] = {0},
parameter int unsigned NrRgprPorts = 2,
parameter type hartid_t = logic,
parameter type id_t = logic,
parameter type x_issue_req_t = logic,
parameter type x_issue_resp_t = logic,
parameter type x_register_t = logic,
parameter type registers_t = logic
) (
input logic clk_i,
input logic rst_ni,
Expand Down Expand Up @@ -53,7 +53,7 @@ module instr_decoder
issue_resp_o.writeback = '0;
issue_resp_o.register_read = '0;
registers_o = '0;
opcode_o = ILLEGAL;
opcode_o = opcode_t'(0); // == ILLEGAL see cvxif_instr_pkg.sv
hartid_o = '0;
id_o = '0;
rd_o = '0;
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38 changes: 19 additions & 19 deletions core/cvxif_issue_register_commit_if_driver.sv
Original file line number Diff line number Diff line change
Expand Up @@ -15,29 +15,29 @@ module cvxif_issue_register_commit_if_driver #(
parameter type x_commit_t = logic
) (
// CVA6 inputs
input logic clk_i,
input logic rst_ni,
input logic flush_i,
input logic [ CVA6Cfg.XLEN-1:0] hart_id_i,
input logic clk_i,
input logic rst_ni,
input logic flush_i,
input logic [CVA6Cfg.XLEN-1:0] hart_id_i,
// CVXIF Issue interface
input logic issue_ready_i,
input x_issue_resp_t issue_resp_i,
output logic issue_valid_o,
output x_issue_req_t issue_req_o,
input logic issue_ready_i,
input x_issue_resp_t issue_resp_i,
output logic issue_valid_o,
output x_issue_req_t issue_req_o,
// CVXIF Register interface
input logic register_ready_i,
output logic register_valid_o,
output x_register_t register_o,
input logic register_ready_i,
output logic register_valid_o,
output x_register_t register_o,
// CVXIF Commit interface
output logic commit_valid_o,
output x_commit_t commit_o,
output logic commit_valid_o,
output x_commit_t commit_o,
// IRO in/out
input logic valid_i,
input logic [ 31:0] x_off_instr_i,
input logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_trans_id_i,
input logic [ CVA6Cfg.NrRgprPorts-1:0][CVA6Cfg.XLEN-1:0] register_i,
input logic [ CVA6Cfg.NrRgprPorts-1:0] rs_valid_i,
output logic cvxif_busy_o
input logic valid_i,
input logic [31:0] x_off_instr_i,
input logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_trans_id_i,
input [(CVA6Cfg.NrRgprPorts/CVA6Cfg.NrIssuePorts)-1:0][CVA6Cfg.XLEN-1:0] register_i,
input logic [(CVA6Cfg.NrRgprPorts/CVA6Cfg.NrIssuePorts)-1:0] rs_valid_i,
output logic cvxif_busy_o
);
// X_ISSUE_REGISTER_SPLIT = 0 : Issue and register transactions are synchrone
// Mandatory assignement
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2 changes: 1 addition & 1 deletion core/include/build_config_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -167,7 +167,7 @@ package build_config_pkg;
cfg.VpnLen = VpnLen;
cfg.PtLevels = PtLevels;

cfg.X_NUM_RS = cfg.NrRgprPorts;
cfg.X_NUM_RS = cfg.NrRgprPorts / cfg.NrIssuePorts;
cfg.X_ID_WIDTH = cfg.TRANS_ID_BITS;
cfg.X_RFR_WIDTH = cfg.XLEN;
cfg.X_RFW_WIDTH = cfg.XLEN;
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