Skip to content

Commit

Permalink
Connect the new AXI agent with CVA6 (#2182)
Browse files Browse the repository at this point in the history
  • Loading branch information
@AEzzejjari
AEzzejjari authored Jun 3, 2024
1 parent ba6262a commit 1c828c0
Show file tree
Hide file tree
Showing 7 changed files with 204 additions and 168 deletions.
2 changes: 1 addition & 1 deletion verif/core-v-verif
Submodule core-v-verif updated 29 files
+20 −2 lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_agent.sv
+107 −480 lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_amo_synchronizer.sv
+279 −0 lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_covg.sv
+299 −142 lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_drv.sv
+0 −274 lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_ext_synchronizer.sv
+653 −189 lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_mon.sv
+34 −71 lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_seq_item_logger.sv
+461 −340 lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_synchronizer.sv
+21 −11 lib/uvm_agents/uvma_axi5/src/comps/uvma_axi_vsqr.sv
+174 −0 lib/uvm_agents/uvma_axi5/src/obj/pure_agent_cfg.sv
+72 −41 lib/uvm_agents/uvma_axi5/src/obj/uvma_axi_cfg.sv
+1 −1 lib/uvm_agents/uvma_axi5/src/seq/uvma_axi_base_seq.sv
+0 −140 lib/uvm_agents/uvma_axi5/src/seq/uvma_axi_base_seq_item.sv
+0 −1 lib/uvm_agents/uvma_axi5/src/seq/uvma_axi_seq_lib.sv
+0 −98 lib/uvm_agents/uvma_axi5/src/seq/uvma_axi_slv_base_seq.sv
+249 −259 lib/uvm_agents/uvma_axi5/src/seq/uvma_axi_slv_seq.sv
+0 −118 lib/uvm_agents/uvma_axi5/src/seq/uvma_axi_slv_seq_item.sv
+1,036 −73 lib/uvm_agents/uvma_axi5/src/seq/uvma_axi_transaction.sv
+210 −0 lib/uvm_agents/uvma_axi5/src/seq/uvma_axi_transaction_cfg.sv
+2 −2 lib/uvm_agents/uvma_axi5/src/uvma_axi_amo_assert.sv
+1 −1 lib/uvm_agents/uvma_axi5/src/uvma_axi_ar_assert.sv
+3 −3 lib/uvm_agents/uvma_axi5/src/uvma_axi_assert.sv
+1 −1 lib/uvm_agents/uvma_axi5/src/uvma_axi_aw_assert.sv
+96 −65 lib/uvm_agents/uvma_axi5/src/uvma_axi_intf.sv
+0 −35 lib/uvm_agents/uvma_axi5/src/uvma_axi_macros.sv
+14 −14 lib/uvm_agents/uvma_axi5/src/uvma_axi_pkg.sv
+138 −62 lib/uvm_agents/uvma_axi5/src/uvma_axi_tdefs.sv
+2 −1 mk/uvmt/vcs.mk
+2 −1 mk/uvmt/vsim.mk
93 changes: 57 additions & 36 deletions verif/env/uvme/cov/uvme_axi_covg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,25 +22,25 @@ covergroup cg_axi_w_channel(string name)
option.per_instance = 1;
option.name = name;

awready_to_valid: coverpoint (item.aw_delay) {
awready_to_valid: coverpoint (item.ready_delay_cycle_chan_ax) {
bins dly[] = {[0:16]};
}

wready_to_valid: coverpoint (item.w_data_trs[0].w_delay) {
wready_to_valid: coverpoint (item.ready_delay_cycle_chan_w[0]) {
bins dly[] = {[0:16]};
}

awsize: coverpoint (item.aw_size){
awsize: coverpoint (item.m_size){
bins size[] = {[0:3]};
ignore_bins IGN_SIZE3 = {3} iff(uvme_cva6_pkg::XLEN == 32);
}

awlock: coverpoint (item.aw_lock){
awlock: coverpoint (item.m_lock){
bins lock[] = {[0:1]};
ignore_bins IGN_EXCLUSIVE = {1} iff(!RVA);
}

wstrb: coverpoint (item.w_data_trs[0].w_strb) {
wstrb: coverpoint (item.m_wstrb[0]) {
bins strb1 = {1};
bins strb2 = {2};
bins strb3 = {3};
Expand Down Expand Up @@ -72,12 +72,12 @@ covergroup cg_axi_b_channel(string name)
option.per_instance = 1;
option.name = name;

bid: coverpoint (item.b_id){
bid: coverpoint (item.m_id){
bins one = {[1:3]} iff(!hpdcache);
illegal_bins ILLEGAL_BINS = {2} iff(!hpdcache);
ignore_bins IGN_EXID = {3} iff(!RVA && !hpdcache);
}
bresp: coverpoint (item.b_resp){
bresp: coverpoint (item.m_resp[0]){
bins zero = {0};
bins one = {1};
bins two = {2};
Expand All @@ -93,23 +93,23 @@ covergroup cg_axi_ar_channel(string name)
option.per_instance = 1;
option.name = name;

arid: coverpoint (item.ar_id) {
arid: coverpoint (item.m_id) {
bins ID[] = {[0:1]} iff(!hpdcache);
}

arlen: coverpoint (item.ar_len) {
arlen: coverpoint (item.m_len) {
bins LEN[] = {[0:1]};
}

arsize: coverpoint (item.ar_size) {
bins SIZE[] = {[0:3]} iff(item.ar_len == 0);
arsize: coverpoint (item.m_size) {
bins SIZE[] = {[0:3]} iff(item.m_len == 0);
}

arready_to_valid: coverpoint (item.ar_delay) {
arready_to_valid: coverpoint (item.ready_delay_cycle_chan_ax) {
bins dly[] = {[0:16]};
}

arlock: coverpoint (item.ar_lock){
arlock: coverpoint (item.m_lock){
bins lock[] = {[0:1]};
ignore_bins IGN_EXCLUSIVE = {1} iff(!RVA);
}
Expand All @@ -136,15 +136,15 @@ covergroup cg_axi_r_channel(string name)
option.per_instance = 1;
option.name = name;

rid: coverpoint (item.r_data_trs[index].r_id) {
rid: coverpoint (item.m_id) {
bins ID[] = {[0:3]} iff(!hpdcache);
illegal_bins ILLEGAL_BINS = {2} iff(!hpdcache);
ignore_bins IGN_EXID = {3} iff(!RVA && !hpdcache);
}

rlast: coverpoint (item.r_data_trs[index].r_last);
rlast: coverpoint (item.m_last[index]);

rresp: coverpoint (item.r_data_trs[index].r_resp){
rresp: coverpoint (item.m_resp[index]){
bins zero = {0};
bins one = {1};
bins two = {2};
Expand All @@ -168,7 +168,10 @@ class uvme_axi_covg_c extends uvm_component;
bit HPDCache;

// TLM
uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_resp_fifo;
uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_aw_req_fifo;
uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_b_resp_fifo;
uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_ar_req_fifo;
uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_r_resp_fifo;

// Covergroup instances
cg_axi_w_channel w_axi_cg;
Expand Down Expand Up @@ -229,7 +232,10 @@ function void uvme_axi_covg_c::build_phase(uvm_phase phase);
RVA = cfg.ext_a_supported;
HPDCache = cfg.HPDCache_supported;

uvme_axi_cov_resp_fifo = new("uvme_axi_cov_resp_fifo" , this);
uvme_axi_cov_b_resp_fifo = new("uvme_axi_cov_b_resp_fifo" , this);
uvme_axi_cov_r_resp_fifo = new("uvme_axi_cov_r_resp_fifo" , this);
uvme_axi_cov_ar_req_fifo = new("uvme_axi_cov_ar_req_fifo" , this);
uvme_axi_cov_aw_req_fifo = new("uvme_axi_cov_aw_req_fifo" , this);

w_axi_cg = new("w_axi_cg");
b_axi_cg = new("b_axi_cg");
Expand All @@ -244,25 +250,40 @@ task uvme_axi_covg_c::run_phase(uvm_phase phase);
`uvm_info(get_type_name(), $sformatf("cov_model_enabled = %d", cfg.cov_model_enabled), UVM_HIGH)
`uvm_info(get_type_name(), $sformatf("ATOMIC ENABLE = %d", RVA), UVM_HIGH)
forever begin
uvma_axi_transaction_c resp_item;

uvme_axi_cov_resp_fifo.get(resp_item);
case (resp_item.access_type)
UVMA_AXI_ACCESS_WRITE : begin

w_axi_cg.sample(resp_item, RVA);
b_axi_cg.sample(resp_item, RVA, HPDCache);

end
UVMA_AXI_ACCESS_READ : begin

ar_axi_cg.sample(resp_item, RVA, HPDCache);
for(int i = 0; i <= resp_item.ar_len; i++) begin
r_axi_cg.sample(resp_item, i, RVA, HPDCache);
end

uvma_axi_transaction_c aw_item;
uvma_axi_transaction_c b_item;
uvma_axi_transaction_c ar_item;
uvma_axi_transaction_c r_item;

fork
uvme_axi_cov_b_resp_fifo.get(b_item);
uvme_axi_cov_r_resp_fifo.get(r_item);
uvme_axi_cov_ar_req_fifo.get(ar_item);
uvme_axi_cov_aw_req_fifo.get(aw_item);
join_any
disable fork;

if(aw_item != null) begin
`uvm_info(get_type_name(), $sformatf("WRITE REQ ITEM DETECTED"), UVM_LOW)
w_axi_cg.sample(aw_item, RVA);
end

if(b_item != null) begin
`uvm_info(get_type_name(), $sformatf("WRITE RESP ITEM DETECTED"), UVM_LOW)
b_axi_cg.sample(b_item, RVA, HPDCache);
end

if(ar_item != null) begin
`uvm_info(get_type_name(), $sformatf("READ ADDRESS ITEM DETECTED"), UVM_LOW)
ar_axi_cg.sample(ar_item, RVA, HPDCache);
end

if(r_item != null) begin
`uvm_info(get_type_name(), $sformatf("READ DATA ITEM DETECTED"), UVM_LOW)
for(int i = 0; i <= r_item.m_len; i++) begin
r_axi_cg.sample(r_item, i, RVA, HPDCache);
end
endcase
end

end

Expand Down
Loading

0 comments on commit 1c828c0

Please sign in to comment.