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Unify ZiCondExtEn flag
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Signed-off-by: Florian Zaruba <[email protected]>
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zarubaf committed Sep 19, 2023
1 parent 468fc66 commit 193184f
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Showing 4 changed files with 6 additions and 6 deletions.
2 changes: 1 addition & 1 deletion core/alu.sv
Original file line number Diff line number Diff line change
Expand Up @@ -302,7 +302,7 @@ module alu import ariane_pkg::*; #(
default: ; // default case to suppress unique warning
endcase
end
if (CVA6Cfg.RCONDEXT) begin
if (CVA6Cfg.ZiCondExtEn) begin
unique case (fu_data_i.operation)
CZERO_EQZ : result_o = (|fu_data_i.operand_b) ? fu_data_i.operand_a : '0; // move zero to rd if rs2 is equal to zero else rs1
CZERO_NEZ : result_o = (|fu_data_i.operand_b) ? '0 : fu_data_i.operand_a; // move zero to rd if rs2 is nonzero else rs1
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2 changes: 1 addition & 1 deletion core/cva6.sv
Original file line number Diff line number Diff line change
Expand Up @@ -177,7 +177,7 @@ module cva6 import ariane_pkg::*; #(
CVA6Cfg.RVC,
CVA6Cfg.XFVec,
CVA6Cfg.CvxifEn,
CVA6Cfg.RCONDEXT,
CVA6Cfg.ZiCondExtEn,
// Extended
bit'(RVF),
bit'(RVD),
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4 changes: 2 additions & 2 deletions core/decoder.sv
Original file line number Diff line number Diff line change
Expand Up @@ -580,7 +580,7 @@ module decoder import ariane_pkg::*; #(
end
endcase
end
if (CVA6Cfg.RCONDEXT) begin
if (CVA6Cfg.ZiCondExtEn) begin
unique case ({instr.rtype.funct7, instr.rtype.funct3})
//Conditional move
{7'b000_0111, 3'b101}: instruction_o.op = ariane_pkg::CZERO_EQZ; // czero.eqz
Expand All @@ -591,7 +591,7 @@ module decoder import ariane_pkg::*; #(
endcase
end
//VCS coverage on
unique case ({ariane_pkg::BITMANIP, CVA6Cfg.RCONDEXT})
unique case ({ariane_pkg::BITMANIP, CVA6Cfg.ZiCondExtEn})
2'b00 : illegal_instr = illegal_instr_non_bm;
2'b01 : illegal_instr = illegal_instr_non_bm & illegal_instr_zic;
2'b10 : illegal_instr = illegal_instr_non_bm & illegal_instr_bm;
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4 changes: 2 additions & 2 deletions core/include/config_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@ package config_pkg;
bit RVC;
bit XFVec;
bit CvxifEn;
bit RCONDEXT;
bit ZiCondExtEn;
// Calculated
bit RVF;
bit RVD;
Expand Down Expand Up @@ -117,7 +117,7 @@ package config_pkg;
RVC: bit'(1),
XFVec: bit'(0),
CvxifEn: bit'(1),
EnableZiCond: bit'(0),
ZiCondExtEn: bit'(0),
// Extended
RVF: bit'(0),
RVD: bit'(0),
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