[riscv-config] Update riscv-config tool, CV32A65X specs and the rende…

…ring of CSRs. (#2270)

config/gen_from_riscv_config/scripts/libs/csr_updater.py

@@ -1,6 +1,7 @@
 import re
 import yaml
 
+
 def csr_recursive_update(original_dict, csr_update):
     """
     Gets the data of the RISC-V Config Yaml file and
@@ -14,14 +15,16 @@ def csr_recursive_update(original_dict, csr_update):
         if key in original_dict:
             if isinstance(value, dict) and isinstance(original_dict[key], dict):
                 # If both are dicts, recurse
-                if key == 'type':
+                if key == "type":
                     # Replace the entire type dictionary
                     original_dict[key] = value
                 else:
                     csr_recursive_update(original_dict[key], value)
             else:
                 # Replace the original value with the update value
                 original_dict[key] = value
+
+
 def csr_formatter(srcfile, modifile):
     # Read original dictionary from YAML source file
     with open(srcfile, "r", encoding="utf-8") as file:
@@ -31,7 +34,7 @@ def csr_formatter(srcfile, modifile):
     if modifile is not None:
         with open(modifile, "r", encoding="utf-8") as file:
             updated_values = yaml.safe_load(file)
-    
+
     # Update original_dict with values from updated_values recursively
     csr_recursive_update(original_dict["hart0"], updated_values)
 

config/gen_from_riscv_config/updaters/cv32a65x/csr_updater.yaml

@@ -3,11 +3,6 @@
 #   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 #   Author: Abdessamii Oukalrazqou
 
-misa:
-    rv32:
-        mxl:
-            type:
-                ro_constant: 0x1
 mip:
     rv32:
         meip:
@@ -18,19 +13,7 @@ mip:
             type:
                 ro_variable:
                       - 0:1              
-mstatush:
-    address: 784      
 
-mcountinhibit: 
-    rv32 : 
-        accessible : false
-
-#  Range control
-pmpaddr : 
-    range: 16
-
-pmpcfg :
-    range : 4
  # Exclude mode 
 exclude :         
    key : priv_mode       

config/riscv-config/cv32a65x/generated/isa_gen.yaml

@@ -90,8 +90,9 @@ hart0:
                     warl:
                         dependency_fields: []
                         legal:
-             # All bits writable (first value of bitmask w/o cleared bits)
-                          - base[29:0] bitmask [0x3FFFFFFF, 0x00000000]
+             # The 30 bits of 'base' are suffixed with 2'b00
+             # ==> all values are legal, alignment 4 bytes is implied
+                          - base[29:0] in [0x00000000:0x3FFFFFFF]
                         wr_illegal:
                           - Unchanged
                 description: Vector base address.
@@ -105,6 +106,7 @@ hart0:
                     warl:
                         dependency_fields: []
                         legal:
+             # Only Direct mode.
                           - mode[1:0] in [0x0]
                         wr_illegal:
                           - Unchanged
@@ -334,9 +336,9 @@ hart0:
                 lsb: 23
         rv64:
             accessible: false
-        description: The mstatus register keeps track of and controls the hart’s current
+        description: The mstatus register keeps track of and controls the hart's current
             operating state.
-        address: 768
+        address: 0x300
         priv_mode: M
     mip:
         reset-val: 0
@@ -711,6 +713,23 @@ hart0:
             hardware thread running the code.
         address: 3860
         priv_mode: M
+    mconfigptr:
+        rv32:
+            accessible: true
+            type:
+                ro_constant: 0x0
+            fields: []
+            shadow:
+            shadow_type: rw
+            msb: 31
+            lsb: 0
+        rv64:
+            accessible: false
+        reset-val: 0x0
+        description: MXLEN-bit read-only register that holds the physical address
+            of a configuration data structure.
+        address: 0xF15
+        priv_mode: M
     mscratch:
         rv32:
             accessible: true
@@ -1692,14 +1711,7 @@ hart0:
         priv_mode: M
     mcountinhibit:
         rv32:
-            accessible: true
-            type:
-                ro_constant: 0x0
-            fields: []
-            shadow:
-            shadow_type: rw
-            msb: 31
-            lsb: 0
+            accessible: false
         rv64:
             accessible: false
         reset-val: 0x0
@@ -3515,7 +3527,7 @@ hart0:
             accessible: false
         description: The mstatush register keeps track of and controls the hart’s
             current operating state.
-        address: 768
+        address: 0x310
         priv_mode: M
         reset-val: 0
     mideleg:

config/riscv-config/cv32a65x/spec/isa_spec.yaml

@@ -56,8 +56,9 @@ hart0: &hart0
          warl:
            dependency_fields: []
            legal:
-             # All bits writable (first value of bitmask w/o cleared bits)
-             - base[29:0] bitmask [0x3FFFFFFF, 0x00000000]
+             # The 30 bits of 'base' are suffixed with 2'b00
+             # ==> all values are legal, alignment 4 bytes is implied
+             - base[29:0] in [0x00000000:0x3FFFFFFF]
            wr_illegal:
              - Unchanged
      mode:
@@ -66,6 +67,7 @@ hart0: &hart0
          warl:
            dependency_fields: []
            legal:
+             # Only Direct mode.
              - mode[1:0] in [0x0]
            wr_illegal:
              - Unchanged
@@ -250,6 +252,14 @@ hart0: &hart0
     rv64:
       accessible: false
     reset-val: 0x00
+  mconfigptr:
+    rv32:
+      accessible: true
+      type:
+         ro_constant: 0x0
+    rv64:
+      accessible: false
+    reset-val: 0x0
   mscratch:
     rv32:
       accessible: true
@@ -729,9 +739,7 @@ hart0: &hart0
     reset-val: 0x0
   mcountinhibit:
     rv32:
-      accessible: true
-      type:
-        ro_constant: 0x0
+      accessible: false
     rv64:
       accessible: false
     reset-val: 0x0

vendor/patches/riscv/riscv-config/0004-fix-mstatush-and-nonascii-chars.patch

@@ -0,0 +1,25 @@
+diff --git a/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml b/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml
+index a7536375f..27e88d16f 100644
+--- a/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml
++++ b/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml
+@@ -523,9 +523,9 @@ hart_schema:
+       schema:
+         description:
+           type: string
+-          default: The mstatus register keeps track of and controls the hart’s current
++          default: The mstatus register keeps track of and controls the hart's current
+             operating state.
+-        address: {type: integer, default: 768, allowed: [768]}
++        address: {type: integer, default: 0x300, allowed: [0x300]}
+         priv_mode: {type: string, default: M, allowed: [M]}
+         reset-val:
+           type: integer
+@@ -1506,7 +1506,7 @@ hart_schema:
+           type: string
+           default: The mstatush register keeps track of and controls the hart’s current
+             operating state.
+-        address: {type: integer, default: 768, allowed: [768]}
++        address: {type: integer, default: 0x310, allowed: [0x310]}
+         priv_mode: {type: string, default: M, allowed: [M]}
+         reset-val:
+           type: integer

vendor/patches/riscv/riscv-config/0005-add-csr-schema-for-mconfigptr.patch

@@ -0,0 +1,60 @@
+diff --git a/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml b/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml
+index 27e88d16f..9c67bbcb7 100644
+--- a/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml
++++ b/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml
+@@ -1819,6 +1819,55 @@ hart_schema:
+               default: true
+               check_with: rv64_check
+           default: {accessible: false}
++    mconfigptr:
++      type: dict
++      schema:
++        description:
++          type: string
++          default: MXLEN-bit read-only register that holds the physical address
++            of a configuration data structure.
++        address: {type: integer, default: 0xF15, allowed: [0xF15]}
++        priv_mode: {type: string, default: M, allowed: [M]}
++        reset-val:
++          type: integer
++          default: 0
++          check_with: max_length
++        rv32:
++          type: dict
++          schema:
++            fields: {type: list, default: []}
++            shadow: {type: string, default: , nullable: True}
++            shadow_type: {type: string, default: rw, nullable: True, allowed: ['rw','ro']}
++            msb: {type: integer, default: 31, allowed: [31]}
++            lsb: {type: integer, default: 0, allowed: [0]}
++            type:
++              type: dict
++              schema: {ro_constant: {type: integer, max:  0xFFFFFFFF}}
++              default:
++                ro_constant: 0
++            accessible:
++              type: boolean
++              default: true
++              check_with: rv32_check
++          default: {accessible: false}
++        rv64:
++          type: dict
++          schema:
++            fields: {type: list, default: []}
++            shadow: {type: string, default: , nullable: True}
++            shadow_type: {type: string, default: rw, nullable: True, allowed: ['rw','ro']}
++            msb: {type: integer, default: 63, allowed: [63]}
++            lsb: {type: integer, default: 0, allowed: [0]}
++            type:
++              type: dict
++              schema: {ro_constant: {type: integer, max:  0xFFFFFFFFFFFFFFFF}}
++              default:
++                ro_constant: 0
++            accessible:
++              type: boolean
++              default: true
++              check_with: rv64_check
++          default: {accessible: false}
+     mtvec:
+       type: dict
+       schema:

vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml

@@ -523,9 +523,9 @@ hart_schema:
       schema:
         description:
           type: string
-          default: The mstatus register keeps track of and controls the hart’s current
+          default: The mstatus register keeps track of and controls the hart's current
             operating state.
-        address: {type: integer, default: 768, allowed: [768]}
+        address: {type: integer, default: 0x300, allowed: [0x300]}
         priv_mode: {type: string, default: M, allowed: [M]}
         reset-val:
           type: integer
@@ -1506,7 +1506,7 @@ hart_schema:
           type: string
           default: The mstatush register keeps track of and controls the hart’s current
             operating state.
-        address: {type: integer, default: 768, allowed: [768]}
+        address: {type: integer, default: 0x310, allowed: [0x310]}
         priv_mode: {type: string, default: M, allowed: [M]}
         reset-val:
           type: integer
@@ -1819,6 +1819,55 @@ hart_schema:
               default: true
               check_with: rv64_check
           default: {accessible: false}
+    mconfigptr:
+      type: dict
+      schema:
+        description:
+          type: string
+          default: MXLEN-bit read-only register that holds the physical address
+            of a configuration data structure.
+        address: {type: integer, default: 0xF15, allowed: [0xF15]}
+        priv_mode: {type: string, default: M, allowed: [M]}
+        reset-val:
+          type: integer
+          default: 0
+          check_with: max_length
+        rv32:
+          type: dict
+          schema:
+            fields: {type: list, default: []}
+            shadow: {type: string, default: , nullable: True}
+            shadow_type: {type: string, default: rw, nullable: True, allowed: ['rw','ro']}
+            msb: {type: integer, default: 31, allowed: [31]}
+            lsb: {type: integer, default: 0, allowed: [0]}
+            type:
+              type: dict
+              schema: {ro_constant: {type: integer, max:  0xFFFFFFFF}}
+              default:
+                ro_constant: 0
+            accessible:
+              type: boolean
+              default: true
+              check_with: rv32_check
+          default: {accessible: false}
+        rv64:
+          type: dict
+          schema:
+            fields: {type: list, default: []}
+            shadow: {type: string, default: , nullable: True}
+            shadow_type: {type: string, default: rw, nullable: True, allowed: ['rw','ro']}
+            msb: {type: integer, default: 63, allowed: [63]}
+            lsb: {type: integer, default: 0, allowed: [0]}
+            type:
+              type: dict
+              schema: {ro_constant: {type: integer, max:  0xFFFFFFFFFFFFFFFF}}
+              default:
+                ro_constant: 0
+            accessible:
+              type: boolean
+              default: true
+              check_with: rv64_check
+          default: {accessible: false}
     mtvec:
       type: dict
       schema: