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Solve some of W240 and W415a warnings increased by PMP entries (#2415)
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@Asmaa-Kassimi
Asmaa-Kassimi authored Aug 1, 2024
1 parent 81671e3 commit 12be3ad
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Showing 4 changed files with 76 additions and 62 deletions.
2 changes: 2 additions & 0 deletions .gitlab-ci/scripts/report_spyglass_lint.py
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Expand Up @@ -94,6 +94,8 @@ def report_spyglass_lint(comparison_results):

report = rb.Report()
report.add_metric(metric)
for value in metric.values:
print(" | ".join(map(str, value)))
report.dump()


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133 changes: 72 additions & 61 deletions core/load_store_unit.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -579,84 +579,94 @@ module load_store_unit
end

if (data_misaligned) begin

if (lsu_ctrl.fu == LOAD) begin
misaligned_exception.cause = riscv::LD_ADDR_MISALIGNED;
misaligned_exception.valid = 1'b1;
if (CVA6Cfg.TvalEn)
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
if (CVA6Cfg.RVH) begin
misaligned_exception.tval2 = '0;
misaligned_exception.tinst = lsu_ctrl.tinst;
misaligned_exception.gva = ld_st_v_i;
case (lsu_ctrl.fu)
LOAD: begin
misaligned_exception.cause = riscv::LD_ADDR_MISALIGNED;
misaligned_exception.valid = 1'b1;
if (CVA6Cfg.TvalEn)
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
if (CVA6Cfg.RVH) begin
misaligned_exception.tval2 = '0;
misaligned_exception.tinst = lsu_ctrl.tinst;
misaligned_exception.gva = ld_st_v_i;
end
end
end
if (lsu_ctrl.fu == STORE) begin
misaligned_exception.cause = riscv::ST_ADDR_MISALIGNED;
misaligned_exception.valid = 1'b1;
if (CVA6Cfg.TvalEn)
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
if (CVA6Cfg.RVH) begin
misaligned_exception.tval2 = '0;
misaligned_exception.tinst = lsu_ctrl.tinst;
misaligned_exception.gva = ld_st_v_i;
STORE: begin

misaligned_exception.cause = riscv::ST_ADDR_MISALIGNED;
misaligned_exception.valid = 1'b1;
if (CVA6Cfg.TvalEn)
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
if (CVA6Cfg.RVH) begin
misaligned_exception.tval2 = '0;
misaligned_exception.tinst = lsu_ctrl.tinst;
misaligned_exception.gva = ld_st_v_i;
end
end
end
default: ;
endcase
end

if (CVA6Cfg.MmuPresent && en_ld_st_translation_i && lsu_ctrl.overflow) begin

if (lsu_ctrl.fu == LOAD) begin
misaligned_exception.cause = riscv::LOAD_PAGE_FAULT;
misaligned_exception.valid = 1'b1;
if (CVA6Cfg.TvalEn)
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
if (CVA6Cfg.RVH) begin
misaligned_exception.tval2 = '0;
misaligned_exception.tinst = lsu_ctrl.tinst;
misaligned_exception.gva = ld_st_v_i;
case (lsu_ctrl.fu)
LOAD: begin
misaligned_exception.cause = riscv::LOAD_PAGE_FAULT;
misaligned_exception.valid = 1'b1;
if (CVA6Cfg.TvalEn)
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
if (CVA6Cfg.RVH) begin
misaligned_exception.tval2 = '0;
misaligned_exception.tinst = lsu_ctrl.tinst;
misaligned_exception.gva = ld_st_v_i;
end
end
end
if (lsu_ctrl.fu == STORE) begin
misaligned_exception.cause = riscv::STORE_PAGE_FAULT;
misaligned_exception.valid = 1'b1;
if (CVA6Cfg.TvalEn)
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
if (CVA6Cfg.RVH) begin
misaligned_exception.tval2 = '0;
misaligned_exception.tinst = lsu_ctrl.tinst;
misaligned_exception.gva = ld_st_v_i;
STORE: begin
misaligned_exception.cause = riscv::STORE_PAGE_FAULT;
misaligned_exception.valid = 1'b1;
if (CVA6Cfg.TvalEn)
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
if (CVA6Cfg.RVH) begin
misaligned_exception.tval2 = '0;
misaligned_exception.tinst = lsu_ctrl.tinst;
misaligned_exception.gva = ld_st_v_i;
end
end
end
default: ;
endcase
end

if (CVA6Cfg.MmuPresent && CVA6Cfg.RVH && en_ld_st_g_translation_i && !en_ld_st_translation_i && lsu_ctrl.g_overflow) begin

if (lsu_ctrl.fu == LOAD) begin
misaligned_exception.cause = riscv::LOAD_GUEST_PAGE_FAULT;
misaligned_exception.valid = 1'b1;
if (CVA6Cfg.TvalEn)
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
if (CVA6Cfg.RVH) begin
misaligned_exception.tval2 = '0;
misaligned_exception.tinst = lsu_ctrl.tinst;
misaligned_exception.gva = ld_st_v_i;
case (lsu_ctrl.fu)
LOAD: begin
misaligned_exception.cause = riscv::LOAD_GUEST_PAGE_FAULT;
misaligned_exception.valid = 1'b1;
if (CVA6Cfg.TvalEn)
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
if (CVA6Cfg.RVH) begin
misaligned_exception.tval2 = '0;
misaligned_exception.tinst = lsu_ctrl.tinst;
misaligned_exception.gva = ld_st_v_i;
end
end
end
if (lsu_ctrl.fu == STORE) begin
misaligned_exception.cause = riscv::STORE_GUEST_PAGE_FAULT;
misaligned_exception.valid = 1'b1;
if (CVA6Cfg.TvalEn)
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
if (CVA6Cfg.RVH) begin
misaligned_exception.tval2 = '0;
misaligned_exception.tinst = lsu_ctrl.tinst;
misaligned_exception.gva = ld_st_v_i;
STORE: begin
misaligned_exception.cause = riscv::STORE_GUEST_PAGE_FAULT;
misaligned_exception.valid = 1'b1;
if (CVA6Cfg.TvalEn)
misaligned_exception.tval = {{CVA6Cfg.XLEN - CVA6Cfg.VLEN{1'b0}}, lsu_ctrl.vaddr};
if (CVA6Cfg.RVH) begin
misaligned_exception.tval2 = '0;
misaligned_exception.tinst = lsu_ctrl.tinst;
misaligned_exception.gva = ld_st_v_i;
end
end
end
default: ;
endcase
end
end


// ------------------
// LSU Control
// ------------------
Expand Down Expand Up @@ -696,3 +706,4 @@ module load_store_unit

endmodule


2 changes: 1 addition & 1 deletion spyglass/reference_summary.rpt
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Original file line number Diff line number Diff line change
Expand Up @@ -119,7 +119,7 @@ WARNING W263 4 A case expression width does not match
case select expression width
WARNING W287b 36 Output port of an instance is not
connected
WARNING W415a 544 Signal may be multiply assigned (beside
WARNING W415a 538 Signal may be multiply assigned (beside
initialization) in the same scope.
WARNING W480 3 Loop index is not of type integer
WARNING W486 2 Shift overflow - some bits may be lost
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1 change: 1 addition & 0 deletions spyglass/sg_setup/cva6/cva6_waiver.awl
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Original file line number Diff line number Diff line change
Expand Up @@ -11,3 +11,4 @@ waive -file_line {$CVA6_REPO_DIR/common/local/util/sram_cache.sv} {85} -severi
waive -file { {$CVA6_REPO_DIR/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv} } -severity { {ERROR} } -rule { {ErrorAnalyzeBBox} }
waive -file { {$CVA6_REPO_DIR/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv} } -severity { {ERROR} } -rule { {SYNTH_5251} }
waive -file { {$CVA6_REPO_DIR/common/local/util/tc_sram_wrapper_cache_techno.sv} } -du { {tc_sram_wrapper_cache_techno} } -severity { {ERROR} } -rule { {ErrorAnalyzeBBox} }
waive -rule { {W240} } -comment {Created by akassimi on 26-Jul-2024 18:36:59}

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