Two minor simulation flow enhancements (#2145)

verif/sim/Makefile

@@ -301,17 +301,15 @@ vcs_uvm_comp:
 	  $(cov-comp-opt) +define+UNSUPPORTED_WITH+ $(isscomp_opts)\
 	  -top uvmt_cva6_tb
 
-vcs_uvm_run:
+vcs_uvm_run: vcs_uvm_comp
 	$(if $(TRACE_FAST), unset VERDI_HOME ;) \
 	cd $(VCS_WORK_DIR)/ && \
 	$(VCS_WORK_DIR)/simv \
 	    $(COMMON_RUN_UVM_FLAGS) \
 	    $(ALL_SIMV_UVM_FLAGS) \
 	    $(cov-run-opt) $(issrun_opts)
 
-vcs-uvm:
-	make vcs_uvm_comp
-	make vcs_uvm_run
+vcs-uvm: vcs_uvm_comp vcs_uvm_run
 	# If present, move default waveform files to log directory.
 	# Keep track of target in waveform file name.
 	[ ! -f $(VCS_WORK_DIR)/novas.vpd  ] || \

verif/sim/cva6.py

@@ -1141,8 +1141,6 @@ def main():
     global test_iteration
     global log_format
     cwd = os.path.dirname(os.path.realpath(__file__))
-    os.environ["RISCV_DV_ROOT"] = cwd + "/dv"
-    os.environ["CVA6_DV_ROOT"]  = cwd + "/../env/corev-dv"
     args = parse_args(cwd)
     # We've parsed all the arguments from the command line; default values
     # can be set in the config file. Read that here.

verif/sim/setup-env.sh

@@ -13,6 +13,10 @@ export RTL_PATH="$ROOT_PROJECT/"
 export TB_PATH="$ROOT_PROJECT/verif/tb/core"
 export TESTS_PATH="$ROOT_PROJECT/verif/tests"
 
+# RISCV-DV & COREV-DV
+export RISCV_DV_ROOT="$ROOT_PROJECT/verif/sim/dv"
+export CVA6_DV_ROOT="$ROOT_PROJECT/verif/env/corev-dv"
+
 if [ -z "$RISCV" ]; then
   echo "Error: RISCV variable undefined."
   return