Mmu unify task 1 - sv32 and sv39 #75
Triggered via pull request
December 15, 2023 16:09
AngelaGonzalezMarino
AngelaGonzalezMarino
synchronize
#1707
Status
Success
Total duration
1m 1s
Artifacts
–
Annotations
2 warnings
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format:
core/mmu_unify/cva6_mmu.sv#L611
[verible-verilog-format] reported by reviewdog 🐶
Raw Output:
core/mmu_unify/cva6_mmu.sv:611:-// ----------
core/mmu_unify/cva6_mmu.sv:612:-// Registers
core/mmu_unify/cva6_mmu.sv:613:-// ----------
core/mmu_unify/cva6_mmu.sv:614:-always_ff @(posedge clk_i or negedge rst_ni) begin
core/mmu_unify/cva6_mmu.sv:615:- if (~rst_ni) begin
core/mmu_unify/cva6_mmu.sv:616:- lsu_vaddr_q <= '0;
core/mmu_unify/cva6_mmu.sv:617:- lsu_req_q <= '0;
core/mmu_unify/cva6_mmu.sv:618:- misaligned_ex_q <= '0;
core/mmu_unify/cva6_mmu.sv:619:- dtlb_pte_q <= '0;
core/mmu_unify/cva6_mmu.sv:620:- dtlb_hit_q <= '0;
core/mmu_unify/cva6_mmu.sv:621:- lsu_is_store_q <= '0;
core/mmu_unify/cva6_mmu.sv:622:- dtlb_is_page_q <= '0;
core/mmu_unify/cva6_mmu.sv:623:- end else begin
core/mmu_unify/cva6_mmu.sv:624:- lsu_vaddr_q <= lsu_vaddr_n;
core/mmu_unify/cva6_mmu.sv:625:- lsu_req_q <= lsu_req_n;
core/mmu_unify/cva6_mmu.sv:626:- misaligned_ex_q <= misaligned_ex_n;
core/mmu_unify/cva6_mmu.sv:627:- dtlb_pte_q <= dtlb_pte_n;
core/mmu_unify/cva6_mmu.sv:628:- dtlb_hit_q <= dtlb_hit_n;
core/mmu_unify/cva6_mmu.sv:629:- lsu_is_store_q <= lsu_is_store_n;
core/mmu_unify/cva6_mmu.sv:630:- dtlb_is_page_q <= dtlb_is_page_n;
core/mmu_unify/cva6_mmu.sv:614:+ // Load/store PMP check
core/mmu_unify/cva6_mmu.sv:615:+ pmp #(
core/mmu_unify/cva6_mmu.sv:616:+ .CVA6Cfg (CVA6Cfg),
core/mmu_unify/cva6_mmu.sv:617:+ .PLEN (riscv::PLEN),
core/mmu_unify/cva6_mmu.sv:618:+ .PMP_LEN (riscv::PLEN - 2),
core/mmu_unify/cva6_mmu.sv:619:+ .NR_ENTRIES(CVA6Cfg.NrPMPEntries)
core/mmu_unify/cva6_mmu.sv:620:+ ) i_pmp_data (
core/mmu_unify/cva6_mmu.sv:621:+ .addr_i (lsu_paddr_o),
core/mmu_unify/cva6_mmu.sv:622:+ .priv_lvl_i (ld_st_priv_lvl_i),
core/mmu_unify/cva6_mmu.sv:623:+ .access_type_i(pmp_access_type),
core/mmu_unify/cva6_mmu.sv:624:+ // Configuration
core/mmu_unify/cva6_mmu.sv:625:+ .conf_addr_i (pmpaddr_i),
core/mmu_unify/cva6_mmu.sv:626:+ .conf_i (pmpcfg_i),
core/mmu_unify/cva6_mmu.sv:627:+ .allow_o (pmp_data_allow)
core/mmu_unify/cva6_mmu.sv:628:+ );
core/mmu_unify/cva6_mmu.sv:629:+
core/mmu_unify/cva6_mmu.sv:630:+ // ----------
core/mmu_unify/cva6_mmu.sv:631:+ // Registers
core/mmu_unify/cva6_mmu.sv:632:+ // ----------
core/mmu_unify/cva6_mmu.sv:633:+ always_ff @(posedge clk_i or negedge rst_ni) begin
core/mmu_unify/cva6_mmu.sv:634:+ if (~rst_ni) begin
core/mmu_unify/cva6_mmu.sv:635:+ lsu_vaddr_q <= '0;
core/mmu_unify/cva6_mmu.sv:636:+ lsu_req_q <= '0;
core/mmu_unify/cva6_mmu.sv:637:+ misaligned_ex_q <= '0;
core/mmu_unify/cva6_mmu.sv:638:+ dtlb_pte_q <= '0;
core/mmu_unify/cva6_mmu.sv:639:+ dtlb_hit_q <= '0;
core/mmu_unify/cva6_mmu.sv:640:+ lsu_is_store_q <= '0;
core/mmu_unify/cva6_mmu.sv:641:+ dtlb_is_page_q <= '0;
core/mmu_unify/cva6_mmu.sv:642:+ end else begin
core/mmu_unify/cva6_mmu.sv:643:+ lsu_vaddr_q <= lsu_vaddr_n;
core/mmu_unify/cva6_mmu.sv:644:+ lsu_req_q <= lsu_req_n;
core/mmu_unify/cva6_mmu.sv:645:+ misaligned_ex_q <= misaligned_ex_n;
core/mmu_unify/cva6_mmu.sv:646:+ dtlb_pte_q <= dtlb_pte_n;
core/mmu_unify/cva6_mmu.sv:647:+ dtlb_hit_q <= dtlb_hit_n;
core/mmu_unify/cva6_mmu.sv:648:+ lsu_is_store_q <= lsu_is_store_n;
core/mmu_unify/cva6_mmu.sv:649:+ dtlb_is_page_q <= dtlb_is_page_n;
core/mmu_unify/cva6_mmu.sv:650:+ end
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format:
core/mmu_unify/cva6_tlb.sv#L290
[verible-verilog-format] reported by reviewdog 🐶
Raw Output:
core/mmu_unify/cva6_tlb.sv:290:-end
core/mmu_unify/cva6_tlb.sv:291:-
core/mmu_unify/cva6_tlb.sv:292:-// Just for checking
core/mmu_unify/cva6_tlb.sv:293:-function int countSetBits(logic [TLB_ENTRIES-1:0] vector);
core/mmu_unify/cva6_tlb.sv:294:- automatic int count = 0;
core/mmu_unify/cva6_tlb.sv:295:- foreach (vector[idx]) begin
core/mmu_unify/cva6_tlb.sv:296:- count += vector[idx];
core/mmu_unify/cva6_tlb.sv:297:- end
core/mmu_unify/cva6_tlb.sv:298:- return count;
core/mmu_unify/cva6_tlb.sv:299:-endfunction
core/mmu_unify/cva6_tlb.sv:300:-
core/mmu_unify/cva6_tlb.sv:301:-assert property (@(posedge clk_i) (countSetBits(lu_hit) <= 1))
core/mmu_unify/cva6_tlb.sv:302:-else begin
core/mmu_unify/cva6_tlb.sv:303:- $error("More then one hit in TLB!");
core/mmu_unify/cva6_tlb.sv:304:- $stop();
core/mmu_unify/cva6_tlb.sv:305:-end
core/mmu_unify/cva6_tlb.sv:306:-assert property (@(posedge clk_i) (countSetBits(replace_en) <= 1))
core/mmu_unify/cva6_tlb.sv:307:-else begin
core/mmu_unify/cva6_tlb.sv:308:- $error("More then one TLB entry selected for next replace!");
core/mmu_unify/cva6_tlb.sv:309:- $stop();
core/mmu_unify/cva6_tlb.sv:310:-end
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