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Merge pull request #376 from Silabs-ArjanB/ArjanB_csr_address_fix
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Corrected CSR addresses for HWLOOP*, FPREC, UHARTID, PRIVLV.
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@Silabs-ArjanB
Silabs-ArjanB authored Aug 31, 2020
2 parents aa74384 + b89a22a commit cc445cd
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81 changes: 43 additions & 38 deletions rtl/cv32e40p_cs_registers.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -306,12 +306,12 @@ if(PULP_SECURE==1) begin
// read logic
always_comb
begin
casex (csr_addr_i)
case (csr_addr_i)
// fcsr: Floating-Point Control and Status Register (frm + fflags).
CSR_FFLAGS : csr_rdata_int = (FPU == 1) ? {27'b0, fflags_q} : '0;
CSR_FRM : csr_rdata_int = (FPU == 1) ? {29'b0, frm_q} : '0;
CSR_FCSR : csr_rdata_int = (FPU == 1) ? {24'b0, frm_q, fflags_q} : '0;
FPREC : csr_rdata_int = ((FPU == 1) && (PULP_XPULP == 1)) ? {27'b0, fprec_q} : '0; // Optional precision control for FP DIV/SQRT Unit
CSR_FPREC : csr_rdata_int = ((FPU == 1) && (PULP_XPULP == 1)) ? {27'b0, fprec_q} : '0; // Optional precision control for FP DIV/SQRT Unit

// mstatus
CSR_MSTATUS: csr_rdata_int = {
Expand Down Expand Up @@ -445,20 +445,23 @@ if(PULP_SECURE==1) begin
csr_rdata_int = mhpmevent_q[csr_addr_i[4:0]];

// hardware loops (not official)
HWLoop0_START : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_start_i[0];
HWLoop0_END : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_end_i[0] ;
HWLoop0_COUNTER: csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_cnt_i[0] ;
HWLoop1_START : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_start_i[1];
HWLoop1_END : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_end_i[1] ;
HWLoop1_COUNTER: csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_cnt_i[1] ;
CSR_LPSTART0 : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_start_i[0];
CSR_LPEND0 : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_end_i[0] ;
CSR_LPCOUNT0 : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_cnt_i[0] ;
CSR_LPSTART1 : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_start_i[1];
CSR_LPEND1 : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_end_i[1] ;
CSR_LPCOUNT1 : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_cnt_i[1] ;

// PMP config registers
CSR_PMPCFG0: csr_rdata_int = USE_PMP ? pmp_reg_q.pmpcfg_packed[0] : '0;
CSR_PMPCFG1: csr_rdata_int = USE_PMP ? pmp_reg_q.pmpcfg_packed[1] : '0;
CSR_PMPCFG2: csr_rdata_int = USE_PMP ? pmp_reg_q.pmpcfg_packed[2] : '0;
CSR_PMPCFG3: csr_rdata_int = USE_PMP ? pmp_reg_q.pmpcfg_packed[3] : '0;

CSR_PMPADDR_RANGE_X :
CSR_PMPADDR0, CSR_PMPADDR1, CSR_PMPADDR2, CSR_PMPADDR3,
CSR_PMPADDR4, CSR_PMPADDR5, CSR_PMPADDR6, CSR_PMPADDR7,
CSR_PMPADDR8, CSR_PMPADDR9, CSR_PMPADDR10, CSR_PMPADDR11,
CSR_PMPADDR12, CSR_PMPADDR13, CSR_PMPADDR14, CSR_PMPADDR15 :
csr_rdata_int = USE_PMP ? pmp_reg_q.pmpaddr[csr_addr_i[3:0]] : '0;

/* USER CSR */
Expand All @@ -472,14 +475,14 @@ if(PULP_SECURE==1) begin
// utvec: user trap-handler base address
CSR_UTVEC: csr_rdata_int = {utvec_q, 6'h0, utvec_mode_q};
// duplicated mhartid: unique hardware thread id (not official)
UHARTID: csr_rdata_int = !PULP_XPULP ? 'b0 : hart_id_i;
CSR_UHARTID: csr_rdata_int = !PULP_XPULP ? 'b0 : hart_id_i;
// uepc: exception program counter
CSR_UEPC: csr_rdata_int = uepc_q;
// ucause: exception cause
CSR_UCAUSE: csr_rdata_int = {ucause_q[5], 26'h0, ucause_q[4:0]};

// current priv level (not official)
PRIVLV: csr_rdata_int = !PULP_XPULP ? 'b0 : {30'h0, priv_lvl_q};
CSR_PRIVLV: csr_rdata_int = !PULP_XPULP ? 'b0 : {30'h0, priv_lvl_q};

default:
csr_rdata_int = '0;
Expand All @@ -495,7 +498,7 @@ end else begin //PULP_SECURE == 0
CSR_FFLAGS : csr_rdata_int = (FPU == 1) ? {27'b0, fflags_q} : '0;
CSR_FRM : csr_rdata_int = (FPU == 1) ? {29'b0, frm_q} : '0;
CSR_FCSR : csr_rdata_int = (FPU == 1) ? {24'b0, frm_q, fflags_q} : '0;
FPREC : csr_rdata_int = ((FPU == 1) && (PULP_XPULP == 1)) ? {27'b0, fprec_q} : '0; // Optional precision control for FP DIV/SQRT Unit
CSR_FPREC : csr_rdata_int = ((FPU == 1) && (PULP_XPULP == 1)) ? {27'b0, fprec_q} : '0; // Optional precision control for FP DIV/SQRT Unit
// mstatus: always M-mode, contains IE bit
CSR_MSTATUS: csr_rdata_int = {
14'b0,
Expand Down Expand Up @@ -622,18 +625,18 @@ end else begin //PULP_SECURE == 0
csr_rdata_int = mhpmevent_q[csr_addr_i[4:0]];

// hardware loops (not official)
HWLoop0_START : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_start_i[0] ;
HWLoop0_END : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_end_i[0] ;
HWLoop0_COUNTER : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_cnt_i[0] ;
HWLoop1_START : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_start_i[1] ;
HWLoop1_END : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_end_i[1] ;
HWLoop1_COUNTER : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_cnt_i[1] ;
CSR_LPSTART0 : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_start_i[0] ;
CSR_LPEND0 : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_end_i[0] ;
CSR_LPCOUNT0 : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_cnt_i[0] ;
CSR_LPSTART1 : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_start_i[1] ;
CSR_LPEND1 : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_end_i[1] ;
CSR_LPCOUNT1 : csr_rdata_int = !PULP_XPULP ? 'b0 : hwlp_cnt_i[1] ;

/* USER CSR */
// dublicated mhartid: unique hardware thread id (not official)
UHARTID: csr_rdata_int = !PULP_XPULP ? 'b0 : hart_id_i;
CSR_UHARTID: csr_rdata_int = !PULP_XPULP ? 'b0 : hart_id_i;
// current priv level (not official)
PRIVLV: csr_rdata_int = !PULP_XPULP ? 'b0 : {30'h0, priv_lvl_q};
CSR_PRIVLV: csr_rdata_int = !PULP_XPULP ? 'b0 : {30'h0, priv_lvl_q};
default:
csr_rdata_int = '0;
endcase
Expand Down Expand Up @@ -675,15 +678,15 @@ if(PULP_SECURE==1) begin

if (FPU == 1) if (fflags_we_i) fflags_n = fflags_i | fflags_q;

casex (csr_addr_i)
case (csr_addr_i)
// fcsr: Floating-Point Control and Status Register (frm, fflags, fprec).
CSR_FFLAGS : if (csr_we_int) fflags_n = (FPU == 1) ? csr_wdata_int[C_FFLAG-1:0] : '0;
CSR_FRM : if (csr_we_int) frm_n = (FPU == 1) ? csr_wdata_int[C_RM-1:0] : '0;
CSR_FCSR : if (csr_we_int) begin
fflags_n = (FPU == 1) ? csr_wdata_int[C_FFLAG-1:0] : '0;
frm_n = (FPU == 1) ? csr_wdata_int[C_RM+C_FFLAG-1:C_FFLAG] : '0;
end
FPREC : if (csr_we_int) fprec_n = ((FPU == 1) && (PULP_XPULP == 1)) ? csr_wdata_int[C_PC-1:0] : '0;
CSR_FPREC : if (csr_we_int) fprec_n = ((FPU == 1) && (PULP_XPULP == 1)) ? csr_wdata_int[C_PC-1:0] : '0;

// mstatus: IE bit
CSR_MSTATUS: if (csr_we_int) begin
Expand Down Expand Up @@ -750,22 +753,24 @@ if(PULP_SECURE==1) begin
end

// hardware loops
HWLoop0_START: if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b001; hwlp_regid_o = 1'b0; end
HWLoop0_END: if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b010; hwlp_regid_o = 1'b0; end
HWLoop0_COUNTER: if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b100; hwlp_regid_o = 1'b0; end
HWLoop1_START: if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b001; hwlp_regid_o = 1'b1; end
HWLoop1_END: if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b010; hwlp_regid_o = 1'b1; end
HWLoop1_COUNTER: if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b100; hwlp_regid_o = 1'b1; end

CSR_LPSTART0 : if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b001; hwlp_regid_o = 1'b0; end
CSR_LPEND0 : if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b010; hwlp_regid_o = 1'b0; end
CSR_LPCOUNT0 : if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b100; hwlp_regid_o = 1'b0; end
CSR_LPSTART1 : if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b001; hwlp_regid_o = 1'b1; end
CSR_LPEND1 : if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b010; hwlp_regid_o = 1'b1; end
CSR_LPCOUNT1 : if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b100; hwlp_regid_o = 1'b1; end

// PMP config registers
CSR_PMPCFG0: if (csr_we_int) begin pmp_reg_n.pmpcfg_packed[0] = csr_wdata_int; pmpcfg_we[3:0] = 4'b1111; end
CSR_PMPCFG1: if (csr_we_int) begin pmp_reg_n.pmpcfg_packed[1] = csr_wdata_int; pmpcfg_we[7:4] = 4'b1111; end
CSR_PMPCFG2: if (csr_we_int) begin pmp_reg_n.pmpcfg_packed[2] = csr_wdata_int; pmpcfg_we[11:8] = 4'b1111; end
CSR_PMPCFG3: if (csr_we_int) begin pmp_reg_n.pmpcfg_packed[3] = csr_wdata_int; pmpcfg_we[15:12] = 4'b1111; end

CSR_PMPADDR_RANGE_X :
if (csr_we_int) begin pmp_reg_n.pmpaddr[csr_addr_i[3:0]] = csr_wdata_int; pmpaddr_we[csr_addr_i[3:0]] = 1'b1; end
CSR_PMPADDR0, CSR_PMPADDR1, CSR_PMPADDR2, CSR_PMPADDR3,
CSR_PMPADDR4, CSR_PMPADDR5, CSR_PMPADDR6, CSR_PMPADDR7,
CSR_PMPADDR8, CSR_PMPADDR9, CSR_PMPADDR10, CSR_PMPADDR11,
CSR_PMPADDR12, CSR_PMPADDR13, CSR_PMPADDR14, CSR_PMPADDR15 :
if (csr_we_int) begin pmp_reg_n.pmpaddr[csr_addr_i[3:0]] = csr_wdata_int; pmpaddr_we[csr_addr_i[3:0]] = 1'b1; end


/* USER CSR */
Expand Down Expand Up @@ -957,7 +962,7 @@ end else begin //PULP_SECURE == 0
fflags_n = (FPU == 1) ? csr_wdata_int[C_FFLAG-1:0] : '0;
frm_n = (FPU == 1) ? csr_wdata_int[C_RM+C_FFLAG-1:C_FFLAG] : '0;
end
FPREC : if (csr_we_int) fprec_n = ((FPU == 1) && (PULP_XPULP == 1)) ? csr_wdata_int[C_PC-1:0] : '0;
CSR_FPREC : if (csr_we_int) fprec_n = ((FPU == 1) && (PULP_XPULP == 1)) ? csr_wdata_int[C_PC-1:0] : '0;

// mstatus: IE bit
CSR_MSTATUS: if (csr_we_int) begin
Expand Down Expand Up @@ -1023,12 +1028,12 @@ end else begin //PULP_SECURE == 0
end

// hardware loops
HWLoop0_START: if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b001; hwlp_regid_o = 1'b0; end
HWLoop0_END: if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b010; hwlp_regid_o = 1'b0; end
HWLoop0_COUNTER: if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b100; hwlp_regid_o = 1'b0; end
HWLoop1_START: if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b001; hwlp_regid_o = 1'b1; end
HWLoop1_END: if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b010; hwlp_regid_o = 1'b1; end
HWLoop1_COUNTER: if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b100; hwlp_regid_o = 1'b1; end
CSR_LPSTART0 : if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b001; hwlp_regid_o = 1'b0; end
CSR_LPEND0 : if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b010; hwlp_regid_o = 1'b0; end
CSR_LPCOUNT0 : if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b100; hwlp_regid_o = 1'b0; end
CSR_LPSTART1 : if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b001; hwlp_regid_o = 1'b1; end
CSR_LPEND1 : if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b010; hwlp_regid_o = 1'b1; end
CSR_LPCOUNT1 : if (PULP_XPULP && csr_we_int) begin hwlp_we_o = 3'b100; hwlp_regid_o = 1'b1; end
endcase

// exception controller gets priority over other writes
Expand Down
60 changes: 39 additions & 21 deletions rtl/cv32e40p_decoder.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2638,15 +2638,15 @@ module cv32e40p_decoder import cv32e40p_pkg::*; import cv32e40p_apu_core_pkg::*;
end

// Determine if CSR access is illegal
casex(instr_rdata_i[31:20])
case (instr_rdata_i[31:20])
// Floating point
CSR_FFLAGS,
CSR_FRM,
CSR_FCSR :
if(!FPU) csr_illegal = 1'b1;

// Floating point (custom)
FPREC :
CSR_FPREC :
if(!(FPU && PULP_XPULP)) csr_illegal = 1'b1;

// Writes to read only CSRs results in illegal instruction
Expand Down Expand Up @@ -2738,30 +2738,48 @@ module cv32e40p_decoder import cv32e40p_pkg::*; import cv32e40p_apu_core_pkg::*;
if(!debug_mode_i) csr_illegal = 1'b1;

// Debug Trigger register access
CSR_TSELECT ,
CSR_TDATA1 ,
CSR_TDATA2 ,
CSR_TDATA3 ,
CSR_TINFO ,
CSR_MCONTEXT ,
CSR_SCONTEXT :
CSR_TSELECT,
CSR_TDATA1,
CSR_TDATA2,
CSR_TDATA3,
CSR_TINFO,
CSR_MCONTEXT,
CSR_SCONTEXT :
if(DEBUG_TRIGGER_EN != 1)
csr_illegal = 1'b1;

// Hardware Loop register access
HWLoop0_START,
HWLoop0_END,
HWLoop0_COUNTER,
HWLoop1_START,
HWLoop1_END,
HWLoop1_COUNTER,
UHARTID,
PRIVLV :
// Hardware Loop register, UHARTID, PRIVLV access
CSR_LPSTART0,
CSR_LPEND0,
CSR_LPCOUNT0,
CSR_LPSTART1,
CSR_LPEND1,
CSR_LPCOUNT1,
CSR_UHARTID,
CSR_PRIVLV :
if(!PULP_XPULP) csr_illegal = 1'b1;

// PMP register access
CSR_PMPCFG_RANGE_X,
CSR_PMPADDR_RANGE_X :
CSR_PMPCFG0,
CSR_PMPCFG1,
CSR_PMPCFG2,
CSR_PMPCFG3,
CSR_PMPADDR0,
CSR_PMPADDR1,
CSR_PMPADDR2,
CSR_PMPADDR3,
CSR_PMPADDR4,
CSR_PMPADDR5,
CSR_PMPADDR6,
CSR_PMPADDR7,
CSR_PMPADDR8,
CSR_PMPADDR9,
CSR_PMPADDR10,
CSR_PMPADDR11,
CSR_PMPADDR12,
CSR_PMPADDR13,
CSR_PMPADDR14,
CSR_PMPADDR15 :
if(!USE_PMP) csr_illegal = 1'b1;

// User register access
Expand All @@ -2773,7 +2791,7 @@ module cv32e40p_decoder import cv32e40p_pkg::*; import cv32e40p_apu_core_pkg::*;

default : csr_illegal = 1'b1;

endcase // casex (instr_rdata_i[31:20])
endcase // case (instr_rdata_i[31:20])

// set csr_status for specific CSR register access:
// Causes controller to enter FLUSH
Expand Down
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