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x86/spec-ctrl: Support Intel PSFD for guests
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The Feb 2022 microcode from Intel retrofits AMD's MSR_SPEC_CTRL.PSFD interface
to Sunny Cove (IceLake) and later cores.

Update the MSR_SPEC_CTRL emulation, and expose it to guests.

Signed-off-by: Andrew Cooper <[email protected]>
Reviewed-by: Jan Beulich <[email protected]>
(cherry picked from commit 52ce1c9)
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andyhhp committed Feb 8, 2022
1 parent b8fec3e commit 2d8eade
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Showing 6 changed files with 11 additions and 4 deletions.
2 changes: 2 additions & 0 deletions tools/libs/light/libxl_cpuid.c
Original file line number Diff line number Diff line change
Expand Up @@ -234,6 +234,8 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
{"fsrs", 0x00000007, 1, CPUID_REG_EAX, 11, 1},
{"fsrcs", 0x00000007, 1, CPUID_REG_EAX, 12, 1},

{"intel-psfd", 0x00000007, 2, CPUID_REG_EDX, 0, 1},

{"lahfsahf", 0x80000001, NA, CPUID_REG_ECX, 0, 1},
{"cmplegacy", 0x80000001, NA, CPUID_REG_ECX, 1, 1},
{"svm", 0x80000001, NA, CPUID_REG_ECX, 2, 1},
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1 change: 1 addition & 0 deletions tools/misc/xen-cpuid.c
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Expand Up @@ -199,6 +199,7 @@ static const char *const str_7b1[32] =

static const char *const str_7d2[32] =
{
[ 0] = "intel-psfd",
};

static const struct {
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2 changes: 1 addition & 1 deletion xen/arch/x86/msr.c
Original file line number Diff line number Diff line change
Expand Up @@ -443,7 +443,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val)
uint64_t msr_spec_ctrl_valid_bits(const struct cpuid_policy *cp)
{
bool ssbd = cp->feat.ssbd || cp->extd.amd_ssbd;
bool psfd = cp->extd.psfd;
bool psfd = cp->feat.intel_psfd || cp->extd.psfd;

/*
* Note: SPEC_CTRL_STIBP is specified as safe to use (i.e. ignored)
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7 changes: 5 additions & 2 deletions xen/arch/x86/spec_ctrl.c
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Expand Up @@ -307,11 +307,13 @@ custom_param("pv-l1tf", parse_pv_l1tf);

static void __init print_details(enum ind_thunk thunk, uint64_t caps)
{
unsigned int _7d0 = 0, e8b = 0, tmp;
unsigned int _7d0 = 0, _7d2 = 0, e8b = 0, max = 0, tmp;

/* Collect diagnostics about available mitigations. */
if ( boot_cpu_data.cpuid_level >= 7 )
cpuid_count(7, 0, &tmp, &tmp, &tmp, &_7d0);
cpuid_count(7, 0, &max, &tmp, &tmp, &_7d0);
if ( max >= 2 )
cpuid_count(7, 2, &tmp, &tmp, &tmp, &_7d2);
if ( boot_cpu_data.extended_cpuid_level >= 0x80000008 )
cpuid(0x80000008, &tmp, &e8b, &tmp, &tmp);

Expand Down Expand Up @@ -345,6 +347,7 @@ static void __init print_details(enum ind_thunk thunk, uint64_t caps)
(_7d0 & cpufeat_mask(X86_FEATURE_STIBP)) ? " STIBP" : "",
(e8b & cpufeat_mask(X86_FEATURE_AMD_SSBD)) ||
(_7d0 & cpufeat_mask(X86_FEATURE_SSBD)) ? " SSBD" : "",
(_7d2 & cpufeat_mask(X86_FEATURE_INTEL_PSFD)) ||
(e8b & cpufeat_mask(X86_FEATURE_PSFD)) ? " PSFD" : "",
(_7d0 & cpufeat_mask(X86_FEATURE_L1D_FLUSH)) ? " L1D_FLUSH" : "",
(_7d0 & cpufeat_mask(X86_FEATURE_MD_CLEAR)) ? " MD_CLEAR" : "",
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1 change: 1 addition & 0 deletions xen/include/public/arch-x86/cpufeatureset.h
Original file line number Diff line number Diff line change
Expand Up @@ -300,6 +300,7 @@ XEN_CPUFEATURE(NSCB, 11*32+ 6) /*A Null Selector Clears Base (and
/* Intel-defined CPU features, CPUID level 0x00000007:1.ebx, word 12 */

/* Intel-defined CPU features, CPUID level 0x00000007:2.edx, word 13 */
XEN_CPUFEATURE(INTEL_PSFD, 13*32+ 0) /*A MSR_SPEC_CTRL.PSFD */

#endif /* XEN_CPUFEATURE */

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2 changes: 1 addition & 1 deletion xen/tools/gen-cpuid.py
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Expand Up @@ -287,7 +287,7 @@ def crunch_numbers(state):
# IBRSB/IBRS, and we pass this MSR directly to guests. Treating them
# as dependent features simplifies Xen's logic, and prevents the guest
# from seeing implausible configurations.
IBRSB: [STIBP, SSBD],
IBRSB: [STIBP, SSBD, INTEL_PSFD],
IBRS: [AMD_STIBP, AMD_SSBD, PSFD,
IBRS_ALWAYS, IBRS_FAST, IBRS_SAME_MODE],
AMD_STIBP: [STIBP_ALWAYS],
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