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Modifying tdd_odu_config.xml and fdd_odu_config.xml
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Change-Id: I9bd0ff14aa03fcc0492820ea3280d59aa03de932
Signed-off-by: pborla <[email protected]>
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@pborla
pborla committed Nov 27, 2024
1 parent cb06fa7 commit 3bb3dfe
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Showing 2 changed files with 20 additions and 20 deletions.
20 changes: 10 additions & 10 deletions build/config/fdd_odu_config.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -190,6 +190,16 @@
</TDD_UL_DL_CFG_COMMON>
</SRV_CELL_CFG_COM_SIB>
</SIB1_PARAMS>
<MIB_PARAMS>
<SYS_FRAME_NUM>0</SYS_FRAME_NUM>
<SUB_CARR_SPACE>0</SUB_CARR_SPACE>
<SSB_SC_OFFSET>0</SSB_SC_OFFSET>
<DMRS_TYPEA_POSITION>0</DMRS_TYPEA_POSITION>
<CORESET_0_INDEX>0</CORESET_0_INDEX>
<SEARCHSPACE_0_INDEX>0</SEARCHSPACE_0_INDEX>
<CELL_BARRED>1</CELL_BARRED>
<INTRA_FREQ_RESELECT>1</INTRA_FREQ_RESELECT>
</MIB_PARAMS>
<F1_DU_SRVD_CELL_INFO>
<F1_DU_CELL_INFO>
<F1_CELL_INFO>
Expand Down Expand Up @@ -369,16 +379,6 @@
</F1_BRDCST_PLMN_INFO>
</F1_DU_CELL_INFO>
</F1_DU_SRVD_CELL_INFO>
<MIB_PARAMS>
<SYS_FRAME_NUM>0</SYS_FRAME_NUM>
<SUB_CARR_SPACE>0</SUB_CARR_SPACE>
<SSB_SC_OFFSET>0</SSB_SC_OFFSET>
<DMRS_TYPEA_POSITION>0</DMRS_TYPEA_POSITION>
<CORESET_0_INDEX>0</CORESET_0_INDEX>
<SEARCHSPACE_0_INDEX>0</SEARCHSPACE_0_INDEX>
<CELL_BARRED>1</CELL_BARRED>
<INTRA_FREQ_RESELECT>1</INTRA_FREQ_RESELECT>
</MIB_PARAMS>
<MAC_CELL_CFG>
<CELL_ID>1</CELL_ID>
<CARRIER_CFG>
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20 changes: 10 additions & 10 deletions build/config/tdd_odu_config.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -190,6 +190,16 @@
</TDD_UL_DL_CFG_COMMON>
</SRV_CELL_CFG_COM_SIB>
</SIB1_PARAMS>
<MIB_PARAMS>
<SYS_FRAME_NUM>0</SYS_FRAME_NUM>
<SUB_CARR_SPACE>1</SUB_CARR_SPACE>
<SSB_SC_OFFSET>0</SSB_SC_OFFSET>
<DMRS_TYPEA_POSITION>0</DMRS_TYPEA_POSITION>
<CORESET_0_INDEX>0</CORESET_0_INDEX>
<SEARCHSPACE_0_INDEX>0</SEARCHSPACE_0_INDEX>
<CELL_BARRED>1</CELL_BARRED>
<INTRA_FREQ_RESELECT>1</INTRA_FREQ_RESELECT>
</MIB_PARAMS>
<F1_DU_SRVD_CELL_INFO>
<F1_DU_CELL_INFO>
<F1_CELL_INFO>
Expand Down Expand Up @@ -369,16 +379,6 @@
</F1_BRDCST_PLMN_INFO>
</F1_DU_CELL_INFO>
</F1_DU_SRVD_CELL_INFO>
<MIB_PARAMS>
<SYS_FRAME_NUM>0</SYS_FRAME_NUM>
<SUB_CARR_SPACE>1</SUB_CARR_SPACE>
<SSB_SC_OFFSET>0</SSB_SC_OFFSET>
<DMRS_TYPEA_POSITION>0</DMRS_TYPEA_POSITION>
<CORESET_0_INDEX>0</CORESET_0_INDEX>
<SEARCHSPACE_0_INDEX>0</SEARCHSPACE_0_INDEX>
<CELL_BARRED>1</CELL_BARRED>
<INTRA_FREQ_RESELECT>1</INTRA_FREQ_RESELECT>
</MIB_PARAMS>
<MAC_CELL_CFG>
<CELL_ID>1</CELL_ID>
<CARRIER_CFG>
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