Add 'riscv32' as an alias for riscv

All of the RISC-V support runs on either 32- or 64- bit architectures,
but sometimes users will specific riscv32 or riscv64 explicitly. Allow
this by mapping riscv32 to riscv sources (as is already done for
riscv64).

Signed-off-by: Keith Packard <[email protected]>

newlib/libc/meson.build

@@ -83,6 +83,7 @@ machine_dirs = {
 		 'or1knd': 'or1k',
 		 'powerpc': 'powerpc',
 		 'riscv': 'riscv',
+		 'riscv32': 'riscv',
 		 'riscv64': 'riscv',
 		 'rl78': 'rl78',
 		 'rx': 'rx',

newlib/libc/picolib/meson.build

@@ -34,6 +34,7 @@
 #
 srcs_machine_tls = {
 			'riscv' : ['machine/riscv/tls.c'],
+			'riscv32' : ['machine/riscv/tls.c'],
 			'riscv64' : ['machine/riscv/tls.c'],
 			'arm' : ['machine/arm/tls.c']
 		      }

newlib/libm/meson.build

@@ -41,6 +41,7 @@ libm_machine_dirs = {
 		      'i686' : 'i386',
 		      'nds32' : 'nds32',
 		      'riscv' : 'riscv',
+		      'riscv32' : 'riscv',
 		      'riscv64' : 'riscv',
 		      'spu' : 'spu',
 		      'xtensa': 'xtensa',

picocrt/meson.build

@@ -34,6 +34,7 @@
 #
 src_picocrt_machine = {
 			'riscv' : 'riscv/crt0.c',
+			'riscv32' : 'riscv/crt0.c',
 			'riscv64' : 'riscv/crt0.c',
 			'arm' : 'arm/crt0.c'
 		      }

semihost/meson.build

@@ -34,6 +34,7 @@
 #
 src_semihost_machine = {
 			'riscv' : 'riscv/semihost-riscv.s',
+			'riscv32' : 'riscv/semihost-riscv.s',
 			'riscv64' : 'riscv/semihost-riscv.s',
 			'arm' : 'arm/semihost-arm.c'
 		      }

test-riscv32.ld

@@ -0,0 +1,5 @@
+__flash = 0x80000000;
+__flash_size = 0x00200000;
+__ram = 0x80200000;
+__ram_size = 0x200000;
+__stack_size = 1k;

test-riscv64.ld

@@ -0,0 +1,5 @@
+__flash = 0x80000000;
+__flash_size = 0x00200000;
+__ram = 0x80200000;
+__ram_size = 0x200000;
+__stack_size = 1k;