32-bit MIPS Processor Implementation

This project implements a 32-bit MIPS processor in Verilog HDL targeting the Xilinx Zynq Zybo FPGA board.

Architecture

• 32-bit pipelined processor
• Separate 32-bit instruction and 16-bit data memories (Harvard architecture)
• 32 x 16-bit general purpose registers
• 32-bit program counter

Instruction Set

• R-type (Register-Register)
• I-type (Register-Immediate)
• Arithmetic, logical, load/store, control
• 32-bit fixed length instructions

Pipeline Stages

The processor has the following 5 pipeline stages:

• Fetch instruction (IF)
• Decode and execute instruction (ID/EX)
• Access memory (MEM)
• Write back (WB)
• Update PC for next instruction (PC)

Components

• Control Unit (Finite State Machine)
• Registers
• ALU
• Instruction Memory
• Data Memory

Simulation

The processor was simulated using testbenches to verify the functionality.

Synthesis

The processor RTL code was synthesized targeting the Xilinx Zynq Zybo FPGA board.

Repository Structure

• rtl/ - Contains Verilog code for the processor
• tb/ - Testbenches for simulation
• syn/ - Synthesis scripts
• docs/ - Documentation (architecture, verification plan etc.)

Documentation

• Spec document - Architecture and implementation details
• Verification plan - Testcases and results
• FPGA Resources - Testcases and results