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Misc tweaks and fixes to the interpreter #2125

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@Jaklyy Jaklyy commented Aug 4, 2024

Remake of my prior interpreter pr to separate out the very complex and performance intensive pipelining timing rework from the miscellaneous bugfixes to get something more easily mergeable.

Fixes and features include:

  1. Writeback should be done before jumping with ldm (fixes an edge case with spsr swapping ie. (sp!, {r15}^)
  2. Improvements to Data Abort behavior (timings are untested and very likely wrong though.....)
    (above fixes aid in getting gbarunner3 working!)
  3. Implement bit 15 of the CP15Control register aka. thumb interwork or w/e it's called
  4. Implement the strange and glitchy behavior of certain loads to r15 on the arm9.
  5. Fix the remaining pc stores to be addr+12 instead of addr+8, including "illegal" stores and mcr
  6. improve some instruction timings: msr, mrs, mcr, multiply instructions. (some are knowingly still wrong, at least on a technical level, but a proper implementation would require pipelining, so we'll pass on that for now)
  7. Fix being able to write to unwriteable bits of the PSR/MPU region sizing regs.
  8. fix clz r15 not being a proper jump (not a comprehensive fix as some other instructions still need pc writes to be tested and implemented)
  9. Implement the improved bus width of vram when the vram access scfg bit is set (bit 13)
  10. Caches should be disabled when the MPU is disabled
  11. Improve accuracy of Prefetch aborts: Timing cost for an aborted fetch is more accurate, and the cpu now behaves properly when moving into an un-executable region without a jump. Additionally melonDS no longer stops execution of the rom when jumping to an un-executable exception region. (that last part is extremely intensive though, ig it could be optimized with a simple hack? Though I strongly doubt it really matters?)
  12. Slightly tweak the way IRQs are processed, they are now processed before an instruction is executed, rather than after. Shouldn't make a huge difference but it should be more "technically correct". might also be a very slight speedup? somehow?

i cannot comprehend what is happening currently
cmp and friends with bits 12-15 set to 1 borrow characteristics from their legacy 26 bit p variants
thumb version does nothing of note
also my prior implementation made mrc w/ r15 raise an exception by accident
oops!
pass bools as a single u8 instead and combine thumb and restore cpsr flags since they're mutually exclusive
prefetch aborts should be handled on executing an instruction by a flag set when the instruction is fetched
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4 participants