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MBus Specification

MBus is the next-generation interconnect that enables the millimeter-scale computing class.

MBus is a chip-to-chip bus designed for ultra-constrained systems. MBus is a multi-master bus supporting an arbitrary number of nodes, priority arbitration, efficient acknowledgements, and extensible addressing, with only four wires and consuming only 3.5 pJ/bit/chip.

MBus is power-aware, enabling the design of power-oblivious systems. Individual chips can fully power off and MBus will automatically take care of all the tricky details.

For more information visit mbus.io.

MBus Name and Logo

Use of the MBus name and logo are subject to the MBus Research End User License Agreement.

The agreement is available at http://mbus.io/static/MBus_EULA_v1.0.pdf


Copright 2014 Regents of the University of Michigan

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Specification for MBus. See http://mbus.io for more details.

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