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Special testing process for LVDS TTL #2532

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ARTIQ Pull Request

Description of Changes

Implements special testing process for LVDS TTL - needs it being set so that it has at least one group of inputs and outputs each.

Related Issue

Closes #2287

Type of Changes

Type
✨ New feature

Steps

All Pull Requests

  • Use correct spelling and grammar.

Code Changes

  • Tested with assembly team without giving additional instructions.

default_ttl_out_name, _ = self.ttl_lvds[ttl_out_index]

print("LVDS TTL channels are tested in groups of 4.")
print("You can choose any channel within the group.")
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Would it be better to specify the group (channel % 4), or have it "align" to a group?

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It already does it (?) - if you specify any channel in group ttl0...ttl3, it will select that group.

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As in, instead of asking for a channel, it would ask for a group (instead of ttl3, group 0). Especially here, where a unit of test is essentially a group anyway - you connect the RJ45 cable to one. Then you wouldn't have to calculate the lower boundary either.

It is a bit of a nitpick and functionally wouldn't change anything, but I would consider it being a bit confusing at a first glance.

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I thought about it, but decided that it would confuse the tester more.

@@ -140,18 +140,21 @@ def process_dio(self, rtio_offset, peripheral, num_channels=8):
class_names[peripheral["bank_direction_high"]]
]
channel = count(0)
board = peripheral["board"].lower() if "board" in peripheral else ""
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.lower()?


print(f"*** Testing LVDS TTL")

if len(self.ttl_lvds_ins) == 0:
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if not self.ttl_lvds_ins:

Signed-off-by: Egor Savkin <[email protected]>
If output channel is last, then there is one ports movement less

Signed-off-by: Egor Savkin <[email protected]>
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Proper LVDS TTL testing process needed
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