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Update Bender.yml to produce core trace
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(double declaration of files pending https://github.com/fabianschuiki/bender/issues/40)
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micprog authored and vogelpi committed Nov 26, 2020
1 parent 54f7206 commit 262f820
Showing 1 changed file with 25 additions and 2 deletions.
27 changes: 25 additions & 2 deletions Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,8 @@ package:
name: ibex

sources:
- include_dirs:
- target: not(rtl)
include_dirs:
- rtl
- shared/rtl
files:
Expand All @@ -26,12 +27,34 @@ sources:
- rtl/ibex_core.sv
- shared/rtl/prim_assert.sv
- target: rtl
defines: {RVFI: true}
include_dirs:
- rtl
- shared/rtl
defines:
RVFI: true
files:
- rtl/ibex_pkg.sv
- rtl/ibex_tracer_pkg.sv
- rtl/ibex_tracer.sv
- rtl/ibex_core_tracing.sv
- rtl/ibex_alu.sv
- rtl/ibex_compressed_decoder.sv
- rtl/ibex_controller.sv
- rtl/ibex_cs_registers.sv
- rtl/ibex_counters.sv
- rtl/ibex_decoder.sv
- rtl/ibex_ex_block.sv
- rtl/ibex_id_stage.sv
- rtl/ibex_if_stage.sv
- rtl/ibex_wb_stage.sv
- rtl/ibex_load_store_unit.sv
- rtl/ibex_multdiv_slow.sv
- rtl/ibex_multdiv_fast.sv
- rtl/ibex_prefetch_buffer.sv
- rtl/ibex_fetch_fifo.sv
- rtl/ibex_pmp.sv
- rtl/ibex_core.sv
- shared/rtl/prim_assert.sv
- target: any(rtl, tsmc55, gf22)
files:
- rtl/ibex_register_file_latch.sv
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