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[rtl] Guard against false memory responses for secure configurations #140

[rtl] Guard against false memory responses for secure configurations

[rtl] Guard against false memory responses for secure configurations #140

Triggered via pull request May 16, 2024 15:22
Status Failure
Total duration 56s
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pr_lint.yml

on: pull_request
verible-lint
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1 error and 1 warning
verible-lint
Process completed with exit code 1.
verible-lint: rtl/ibex_ex_block.sv#L208
[verible-verilog-lint] reported by reviewdog 🐶 All generate block statements must have a label [Style: generate-statements] [generate-label] Raw Output: message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"./rtl/ibex_ex_block.sv" range:{start:{line:208 column:12}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}