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Make sure net is valid before setting it as wire LUT output #5772

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Make sure net is valid before setting it as wire LUT output

Make sure net is valid before setting it as wire LUT output #5772

Run time

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Job Run time
Detect code changes
8s
Debug Build (Ubuntu 22.04)
23m 41s
docker_regression_tests
0s
Build w/o Yosys (Ubuntu 22.04)
20m 59s
Build Compatibility: GCC-9 (Ubuntu 22.04)
28m 53s
Build w/o Yosys plugin (Ubuntu 22.04)
30m 2s
Build Compatibility: GCC-10 (Ubuntu 22.04)
29m 51s
No-warning Build (Ubuntu 22.04)
28m 29s
Build w/o test (Ubuntu 22.04)
30m 3s
Build Compatibility: GCC-11 (Ubuntu 22.04)
30m 38s
Build (GCC-11 on Ubuntu 20.04)
35m 16s
Build w/o version number (Ubuntu 22.04)
29m 38s
Build (Clang-10 on Ubuntu 20.04)
21m 39s
Build w/o SWIG support (Ubuntu 22.04)
28m 15s
Build Compatibility: GCC-12 (Ubuntu 22.04)
33m 15s
Build Compatibility: Clang-11 (Ubuntu 22.04)
19m 42s
Build Compatibility: Clang-12 (Ubuntu 22.04)
33m 30s
Build Compatibility: Clang-13 (Ubuntu 22.04)
33m 36s
Build Compatibility: Clang-14 (Ubuntu 22.04)
19m 24s
linux_regression_tests (basic_reg_yosys_only_test)
1m 16s
linux_regression_tests (basic_reg_test)
16m 32s
Build docker image for distribution
1m 29s
linux_regression_tests (fpga_verilog_reg_test)
10m 7s
linux_regression_tests (fpga_bitstream_reg_test)
15m 12s
linux_regression_tests (fpga_sdc_reg_test)
1m 13s
linux_regression_tests (fpga_spice_reg_test)
1m 8s
linux_regression_tests (micro_benchmark_reg_test)
5m 52s
linux_regression_tests (quicklogic_reg_test)
13m 20s
linux_regression_tests (vtr_benchmark_reg_test)
57m 33s
linux_regression_tests (iwls_benchmark_reg_test)
48m 52s
linux_regression_tests (tcl_reg_test)
2m 34s
10h 52m 7s