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[MLIR][ROCDL] Remove patterns for ops supported as intrinsics in the AMDGPU backend #102971
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[MLIR][ROCDL] Remove patterns for ops supported as intrinsics in the …
jsjodin 58f0fc6
Add back patterns for 64-bit math:LogOp and math:ExpOp
jsjodin c94abdc
Fix comment.
jsjodin e88b212
Move log test for better diff.
jsjodin f626a00
Add tests back for f64
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Original file line number | Diff line number | Diff line change |
---|---|---|
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@@ -48,18 +48,20 @@ static void populateOpPatterns(LLVMTypeConverter &converter, | |
void mlir::populateMathToROCDLConversionPatterns(LLVMTypeConverter &converter, | ||
RewritePatternSet &patterns) { | ||
// Handled by mathToLLVM: math::AbsIOp | ||
// Handled by mathToLLVM: math::AbsFIOp | ||
// Handled by mathToLLVM: math::CopySignOp | ||
// Handled by mathToLLVM: math::CountLeadingZerosOp | ||
// Handled by mathToLLVM: math::CountTrailingZerosOp | ||
// Handled by mathToLLVM: math::CgPopOp | ||
// Handled by mathToLLVM: math::ExpOp (32-bit only) | ||
// Handled by mathToLLVM: math::FmaOp | ||
// Handled by mathToLLVM: math::LogOp (32-bit only) | ||
// FIXME: math::IPowIOp | ||
// FIXME: math::FPowIOp | ||
// Handled by mathToLLVM: math::RoundEvenOp | ||
// Handled by mathToLLVM: math::RoundOp | ||
// Handled by mathToLLVM: math::SqrtOp | ||
// Handled by mathToLLVM: math::TruncOp | ||
populateOpPatterns<math::AbsFOp>(converter, patterns, "__ocml_fabs_f32", | ||
"__ocml_fabs_f64"); | ||
populateOpPatterns<math::AcosOp>(converter, patterns, "__ocml_acos_f32", | ||
"__ocml_acos_f64"); | ||
populateOpPatterns<math::AcoshOp>(converter, patterns, "__ocml_acosh_f32", | ||
|
@@ -84,16 +86,14 @@ void mlir::populateMathToROCDLConversionPatterns(LLVMTypeConverter &converter, | |
"__ocml_cosh_f64"); | ||
populateOpPatterns<math::SinhOp>(converter, patterns, "__ocml_sinh_f32", | ||
"__ocml_sinh_f64"); | ||
populateOpPatterns<math::ExpOp>(converter, patterns, "__ocml_exp_f32", | ||
"__ocml_exp_f64"); | ||
populateOpPatterns<math::ExpOp>(converter, patterns, "", "__ocml_exp_f64"); | ||
populateOpPatterns<math::Exp2Op>(converter, patterns, "__ocml_exp2_f32", | ||
"__ocml_exp2_f64"); | ||
populateOpPatterns<math::ExpM1Op>(converter, patterns, "__ocml_expm1_f32", | ||
"__ocml_expm1_f64"); | ||
populateOpPatterns<math::FloorOp>(converter, patterns, "__ocml_floor_f32", | ||
"__ocml_floor_f64"); | ||
populateOpPatterns<math::LogOp>(converter, patterns, "__ocml_log_f32", | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Same note re f64 log |
||
"__ocml_log_f64"); | ||
populateOpPatterns<math::LogOp>(converter, patterns, "", "__ocml_log_f64"); | ||
populateOpPatterns<math::Log10Op>(converter, patterns, "__ocml_log10_f32", | ||
"__ocml_log10_f64"); | ||
populateOpPatterns<math::Log1pOp>(converter, patterns, "__ocml_log1p_f32", | ||
|
@@ -106,8 +106,6 @@ void mlir::populateMathToROCDLConversionPatterns(LLVMTypeConverter &converter, | |
"__ocml_rsqrt_f64"); | ||
populateOpPatterns<math::SinOp>(converter, patterns, "__ocml_sin_f32", | ||
"__ocml_sin_f64"); | ||
populateOpPatterns<math::SqrtOp>(converter, patterns, "__ocml_sqrt_f32", | ||
"__ocml_sqrt_f64"); | ||
populateOpPatterns<math::TanhOp>(converter, patterns, "__ocml_tanh_f32", | ||
"__ocml_tanh_f64"); | ||
populateOpPatterns<math::TanOp>(converter, patterns, "__ocml_tan_f32", | ||
|
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Having disassembled OCML, the double-precision exp isn't actually a direct wrapper around the relevant intrinsic, but I figure that's probably fine
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Correct. We only directly handle the f32 (and I think f16) versions. The f64 versions of the hard operations do not work. We do directly handle llvm.sqrt.f64 as an exception.
Also, none of the trig functions are directly handled (correctly). We do codegen the f32 versions but probably shouldn't
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So what do we do in the case of f32 being handled but f64 not, should we still just call ocml for both or modify the lowering to handle just one of them?
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Modify the lowering to handle just one. The operation + type should be treated like different operations, so emit the working f32 intrinsics and the calls for the nonworking f64
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Okay, I put the lowering for f64 back for log and exp and added the tests back for them as well.