various changes done on an rpi4

arch/vc4/arch.c

@@ -4,22 +4,25 @@
 #include <lk/console_cmd.h>
 #include <lk/reg.h>
 #include <platform/bcm28xx.h>
+#include <kernel/thread.h>
 
 static int cmd_boot_other_core(int argc, const cmd_args *argv);
+static int cmd_testit(int argc, const cmd_args *argv);
 
 static char core2_stack[4096];
 uint32_t core2_stack_top = 0;
 
 STATIC_COMMAND_START
 STATIC_COMMAND("boot_other_core", "boot the 2nd vpu core", &cmd_boot_other_core)
+STATIC_COMMAND("testit", "do some asm tests", &cmd_testit)
 STATIC_COMMAND_END(arch);
 
 void arch_early_init(void) {
   uint32_t r28, sp, sr;
   __asm__ volatile ("mov %0, r28" : "=r"(r28));
   __asm__ volatile ("mov %0, sp" : "=r"(sp));
   __asm__ volatile ("mov %0, sr" : "=r"(sr));
-  dprintf(INFO, "arch_early_init\nr28: 0x%x\nsp: 0x%x\nsr: 0x%x\n", r28, sp, sr);
+  //dprintf(INFO, "arch_early_init\nr28: 0x%x\nsp: 0x%x\nsr: 0x%x\n", r28, sp, sr);
 }
 
 void arch_init(void) {
@@ -37,7 +40,7 @@ void arch_chain_load(void *entry, ulong arg0, ulong arg1, ulong arg2, ulong arg3
     PANIC_UNIMPLEMENTED;
 }
 
-void core2_start();
+void core2_start(void);
 
 static int cmd_boot_other_core(int argc, const cmd_args *argv) {
   core2_stack_top = (core2_stack + sizeof(core2_stack)) - 4;
@@ -50,3 +53,24 @@ void core2_entry() {
   dprintf(INFO, "core2 says hello\n");
   for (;;);
 }
+
+void testit(uint32_t *, uint32_t, uint32_t, uint32_t, uint32_t);
+
+static int cmd_testit(int argc, const cmd_args *argv) {
+  uint32_t target[4];
+  testit(target, 0x11, 0x22, 0x33, 0x44);
+  printf("%x %x %x %x\n", target[0], target[1], target[2], target[3]);
+  return 0;
+}
+
+int vc4_atomic_add(volatile int *ptr, int val) {
+  // TODO
+  //spin_lock_saved_state_t state;
+  //arch_interrupt_save(&state, SPIN_LOCK_FLAG_INTERRUPTS);
+  THREAD_LOCK(state);
+  int old = *ptr;
+  *ptr += val;
+  //arch_interrupt_restore(&state, SPIN_LOCK_FLAG_INTERRUPTS);
+  THREAD_UNLOCK(state);
+  return old;
+}

arch/vc4/include/arch/arch_ops.h

@@ -18,10 +18,10 @@ static inline bool arch_ints_disabled(void) {
   return !(state & 0x40000000);
 }
 
+int vc4_atomic_add(volatile int *ptr, int val);
+
 static inline int atomic_add(volatile int *ptr, int val) {
-  // TODO
-  *ptr += val;
-  return *ptr;
+  return vc4_atomic_add(ptr, val);
 }
 
 static inline int atomic_or(volatile int *ptr, int val) {
@@ -36,7 +36,7 @@ static inline int atomic_swap(volatile int *ptr, int val) {
     return __atomic_exchange_n(ptr, val, __ATOMIC_RELAXED);
 }
 static inline struct thread *get_current_thread(void) {
-  uint32_t thread_reg;
+  struct thread *thread_reg;
   __asm__ volatile("mov %0, r29" : "=r"(thread_reg));
   return thread_reg;
 }
@@ -51,5 +51,6 @@ static inline uint arch_curr_cpu_num(void) {
   uint32_t cpuid;
   __asm__("version %0" : "=r"(cpuid));
   // TODO, one of the bits in the cpuid is the cpu#, dont remember which one
+  // a pdf for an older ARC model says the cpuid contains a 16bit vendor id, 8bit coreid, and 8bit cpuid
   return 0;
 }

arch/vc4/include/arch/arch_thread.h

@@ -4,4 +4,5 @@
 
 struct arch_thread {
   uint32_t sp;
+  uint32_t sr;
 };

arch/vc4/include/arch/spinlock.h

@@ -55,14 +55,17 @@ arch_interrupt_save(spin_lock_saved_state_t *statep, spin_lock_save_flags_t flag
     if (!arch_ints_disabled()) {
         state |= SPIN_LOCK_STATE_RESTORE_IRQ;
         arch_disable_ints();
+        //printf("irq was on, disabled\n");
     }
     *statep = state;
 }
 
 static inline void
 arch_interrupt_restore(spin_lock_saved_state_t old_state, spin_lock_save_flags_t flags) {
-    if (old_state & SPIN_LOCK_STATE_RESTORE_IRQ)
+    if (old_state & SPIN_LOCK_STATE_RESTORE_IRQ) {
+        //printf("restoring ints\n");
         arch_enable_ints();
+    }
 }
 
 

arch/vc4/include/arch/vc4_traps.h

@@ -4,18 +4,19 @@
 
 void fleh_zero(void);
 void fleh_misaligned(void);
-void fleh_dividebyzero();
-void fleh_undefinedinstruction();
-void fleh_forbiddeninstruction();
-void fleh_illegalmemory();
-void fleh_buserror();
-void fleh_floatingpoint();
-void fleh_isp();
-void fleh_dummy();
-void fleh_icache();
-void fleh_veccore();
-void fleh_badl2alias();
-void fleh_breakpoint();
-void fleh_unknown();
-void fleh_irq();
+void fleh_dividebyzero(void);
+void fleh_undefinedinstruction(void);
+void fleh_forbiddeninstruction(void);
+void fleh_illegalmemory(void);
+void fleh_buserror(void);
+void fleh_floatingpoint(void);
+void fleh_isp(void);
+void fleh_dummy(void);
+void fleh_icache(void);
+void fleh_veccore(void);
+void fleh_badl2alias(void);
+void fleh_breakpoint(void);
+void fleh_unknown(void);
+void fleh_irq(void);
+void fleh_swi(void);
 void print_vpu_state(vc4_saved_state_t* pcb);

arch/vc4/intc.c

@@ -19,7 +19,7 @@ struct handlerArgPair irq_handlers[64];
 // it will then push pc and sr onto the new stack
 // it will then read an entry from this vector table, and set the PC to that entry
 // if the highest bit on this addr is set, the cpu will switch into supervisor mode
-irqType __attribute__ ((aligned (512))) vectorTable[144]; // might only need to be 128 entries
+irqType __attribute__ ((aligned (512))) vectorTable[128]; // might only need to be 128 entries
 
 uint8_t irq_stack0[4096];
 
@@ -83,7 +83,7 @@ void intc_init(void) {
   }
   // swi opcode handler
   for (int i=32; i<=63; i++) {
-    vectorTable[i] = (uint32_t)fleh_irq | 1;
+    vectorTable[i] = (uint32_t)fleh_swi;
   }
   // external interrupts
   for (int i=64; i<=127; i++) {
@@ -93,12 +93,12 @@ void intc_init(void) {
   uint32_t irq_sp = (irq_stack0 + sizeof(irq_stack0)) - 4;
   dprintf(INFO, "r28 = 0x%x\nirq_stack0: %p\nsizeof(irq_stack0): %d\n", irq_sp, irq_stack0, sizeof(irq_stack0));
 
-  __asm__ volatile ("mov r28, 0xdeadbeef": :"r"(irq_sp));
+  __asm__ volatile ("mov r28, %0": :"r"(irq_sp));
 
-  *REG32(IC0_VADDR) = vectorTable;
-  *REG32(IC1_VADDR) = vectorTable;
+  *REG32(IC0_VADDR) = (uint32_t)vectorTable;
+  *REG32(IC1_VADDR) = (uint32_t)vectorTable;
 
-  if (*REG32(IC0_VADDR) != vectorTable) {
+  if (((void *)*REG32(IC0_VADDR)) != vectorTable) {
     printf("vector table now at 0x%08x 0x%08x\n", *REG32(IC0_VADDR), (uint32_t)vectorTable);
     panic("vector table failed to install");
   }
@@ -234,3 +234,8 @@ void sleh_irq(vc4_saved_state_t* pcb, uint32_t tp) {
     panic("unknown interrupt source!");
   }
 }
+
+void sleh_swi(vc4_saved_state_t* pcb) {
+  dprintf(INFO, "got SWI\n");
+  print_vpu_state(pcb);
+}

arch/vc4/interrupt.S

@@ -1,6 +1,14 @@
 .macro SaveRegsLower
   stm lr, (--sp)
+  nop
+  nop
+  nop
+  nop
   stm r0-r5, (--sp)
+  nop
+  nop
+  nop
+  nop
 .endm
 
 .macro SaveRegsUpper
@@ -55,3 +63,17 @@ return_from_exception:
   ldm r0-r5, (sp++)
   ld lr, (sp++)
   rti
+
+.global fleh_swi
+fleh_swi:
+  stm lr, (--sp)
+  stm r0-r5, (--sp)
+  stm r6-r15, (--sp)
+  stm r16-r23, (--sp)
+  mov r0, sp
+  bl sleh_swi
+  ldm r16-r23, (sp++)
+  ldm r6-r15, (sp++)
+  ldm r0-r5, (sp++)
+  ld lr, (sp++)
+  rti

arch/vc4/start.S

@@ -1,6 +1,6 @@
 #include <lk/asm.h>
 
-.text
+.section .text.start
 FUNCTION(_start)
 .global _start
 _start:
@@ -20,3 +20,11 @@ core2_start:
   bl core2_entry
 loop2:
   b loop2
+
+.global testit
+testit:
+  st r1, (r0)
+  st r2, (r0+4)
+  st r3, (r0+8)
+  st r4, (r0+12)
+  rts

arch/vc4/thread.c

@@ -9,7 +9,14 @@ void arch_context_switch(thread_t *oldthread, thread_t *newthread) {
   __asm__ volatile ("mov %0, sp" : "=r"(sp));
   //dprintf(INFO, "arch_context_switch\nr28: 0x%x\nsp: 0x%x\n", r28, sp);
   //dprintf(INFO, "switching (%s) -> %p(%s)\n", oldthread->name, newthread->arch.sp, newthread->name);
-  vc4_context_switch(&oldthread->arch.sp, newthread->arch.sp);
+  //dprintf(INFO, "old: %p %s\nSP: 0x%x\nSR: 0x%x\n", oldthread, oldthread->name, oldthread->arch.sp, oldthread->arch.sr);
+  //dprintf(INFO, "new: %p %s\nSP: 0x%x\nSR: 0x%x\n", newthread, newthread->name, newthread->arch.sp, newthread->arch.sr);
+  vc4_context_switch(&oldthread->arch, &newthread->arch);
+  //dprintf(INFO, "switched\n\n");
+}
+
+void boop() {
+  dprintf(INFO, "boop\n");
 }
 
 static inline void push(thread_t *t, uint32_t val) {
@@ -22,20 +29,21 @@ static inline void push(thread_t *t, uint32_t val) {
 static void initial_thread_func(void) __NO_RETURN;
 static void initial_thread_func(void) {
   thread_t *ct = get_current_thread();
-  uint32_t own_sp;
+  uint32_t own_sp, sr;
 
   __asm__ volatile ("mov %0, sp": "=r"(own_sp));
-  dprintf(INFO, "thread %p(%s) starting with sp near 0x%x\n", ct, ct->name, own_sp);
+  //dprintf(INFO, "thread %p(%s) starting with sp near 0x%x\n", ct, ct->name, own_sp);
 
   int ret = ct->entry(ct->arg);
 
   thread_exit(ret);
 }
 
 void arch_thread_initialize(thread_t *t) {
-  printf("thread %p(%s) has a stack of %p+0x%x\n", t, t->name, t->stack, t->stack_size);
+  //printf("thread %p(%s) has a stack of %p+0x%x\n", t, t->name, t->stack, t->stack_size);
   t->arch.sp = (t->stack + t->stack_size) - 4;
-  push(t, &initial_thread_func);
+  __asm__ volatile ("mov %0, sr": "=r"(t->arch.sr));
+  push(t, &initial_thread_func); // lr
   for (int i=6; i<=23; i++) {
     push(t, 0); // r${i}
   }

arch/vc4/thread_asm.S

@@ -1,8 +1,36 @@
 .text
 .global vc4_context_switch
-// r0 is address to save the sp to
-// r1 is the new sp to load
+// r0 is address of the old arch_thread
+// r1 is address of the new arch_thread
 vc4_context_switch:
+  // save all state that is caller saved
+  stm lr, (--sp)
+  stm r6-r15, (--sp)
+  stm r16-r23, (--sp)
+
+
+  // swap stacks
+  st sp, (r0)
+  mov r2, sr
+  st r2, (r0+4)
+
+  ld sp, (r1)
+  mov r3, sp
+  //swi 0
+
+  // restore all state from stack
+  ldm r16-r23, (sp++)
+  ldm r6-r15, (sp++)
+  ldm r0, (sp++)
+  mov lr, r0
+
+  lea r0, vc4_context_switch_finish
+  st r0, (--sp)
+  ld r1, (r1+4) // load saved SR
+  st r1, (--sp)
+  rti
+
+oldvc4_context_switch:
   stm lr, (--sp)
   stm r6-r15, (--sp)
   stm r16-r23, (--sp)
@@ -11,3 +39,6 @@ vc4_context_switch:
   ldm r16-r23, (sp++)
   ldm r6-r15, (sp++)
   ldm pc,(sp++)
+
+vc4_context_switch_finish:
+  rts

arch/vc4/timer.c

@@ -10,7 +10,7 @@ static enum handler_return timer0_irq(void *arg);
 
 lk_bigtime_t current_time_hires(void) {
   //TODO, deal with rollover
-  return (( ((lk_bigtime_t)*REG32(ST_CHI)) << 32) | *REG32(ST_CLO)) / 1000;
+  return ( ((lk_bigtime_t)*REG32(ST_CHI)) << 32) | *REG32(ST_CLO);
 }
 
 lk_time_t current_time(void) {