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Add support for cv32a65x dedicated synthesis (openhwgroup#2178)
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@@ -19,6 +19,7 @@ build/* | |
| /Bender.local | ||
| build/ | ||
| *.vcd | ||
| *.fsdb | ||
| *.log | ||
| *.out | ||
| *.jou | ||
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| @@ -1,4 +1,4 @@ | ||
| cv32a6_embedded: | ||
| gates: 110095 | ||
| cv32a65x: | ||
| gates: 109555 | ||
| gates: 128136 |
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| // Copyright 2018 ETH Zurich and University of Bologna. | ||
| // Copyright and related rights are licensed under the Solderpad Hardware | ||
| // License, Version 0.51 (the "License"); you may not use this file except in | ||
| // compliance with the License. You may obtain a copy of the License at | ||
| // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law | ||
| // or agreed to in writing, software, hardware and materials distributed under | ||
| // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR | ||
| // CONDITIONS OF ANY KIND, either express or implied. See the License for the | ||
| // specific language governing permissions and limitations under the License. | ||
| // | ||
| // Author: Florian Zaruba <[email protected]>, ETH Zurich | ||
| // Michael Schaffner <[email protected]>, ETH Zurich | ||
| // Date: 15.08.2018 | ||
| // Description: SRAM wrapper for FPGA (requires the fpga-support submodule) | ||
| // | ||
| // Note: the wrapped module contains two different implementations for | ||
| // ALTERA and XILINX tools, since these follow different coding styles for | ||
| // inferrable RAMS with byte enable. define `FPGA_TARGET_XILINX or | ||
| // `FPGA_TARGET_ALTERA in your build environment (default is ALTERA) | ||
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| module sram_cache #( | ||
| parameter DATA_WIDTH = 64, | ||
| parameter USER_WIDTH = 1, | ||
| parameter USER_EN = 0, | ||
| parameter NUM_WORDS = 1024, | ||
| parameter SIM_INIT = "none", | ||
| parameter BYTE_ACCESS = 1, | ||
| parameter TECHNO_CUT = 0, | ||
| parameter OUT_REGS = 0 // enables output registers in FPGA macro (read lat = 2) | ||
| )( | ||
| input logic clk_i, | ||
| input logic rst_ni, | ||
| input logic req_i, | ||
| input logic we_i, | ||
| input logic [$clog2(NUM_WORDS)-1:0] addr_i, | ||
| input logic [USER_WIDTH-1:0] wuser_i, | ||
| input logic [DATA_WIDTH-1:0] wdata_i, | ||
| input logic [(DATA_WIDTH+7)/8-1:0] be_i, | ||
| output logic [USER_WIDTH-1:0] ruser_o, | ||
| output logic [DATA_WIDTH-1:0] rdata_o | ||
| ); | ||
| localparam DATA_AND_USER_WIDTH = USER_EN ? DATA_WIDTH + USER_WIDTH : DATA_WIDTH; | ||
| if (TECHNO_CUT) begin : gen_techno_cut | ||
| if (USER_EN > 0) begin | ||
| logic [DATA_WIDTH + USER_WIDTH-1:0] wdata_user; | ||
| logic [DATA_WIDTH + USER_WIDTH-1:0] rdata_user; | ||
| logic [(DATA_WIDTH+7)/8+(DATA_WIDTH+7)/8-1:0] be; | ||
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| always_comb begin | ||
| wdata_user = {wdata_i, wuser_i}; | ||
| be = {be_i, be_i}; | ||
| rdata_o = rdata_user[DATA_AND_USER_WIDTH-1:DATA_WIDTH]; | ||
| ruser_o = rdata_user[USER_WIDTH-1:0]; | ||
| end | ||
| tc_sram_wrapper_cache_techno #( | ||
| .NumWords(NUM_WORDS), // Number of Words in data array | ||
| .DataWidth(DATA_AND_USER_WIDTH),// Data signal width | ||
| .ByteWidth(32'd8), // Width of a data byte | ||
| .NumPorts(32'd1), // Number of read and write ports | ||
| .Latency(32'd1), // Latency when the read data is available | ||
| .SimInit(SIM_INIT), // Simulation initialization | ||
| .BYTE_ACCESS(BYTE_ACCESS), // ACCESS byte or full word | ||
| .PrintSimCfg(1'b0) // Print configuration | ||
| ) i_tc_sram_wrapper ( | ||
| .clk_i ( clk_i ), | ||
| .rst_ni ( rst_ni ), | ||
| .req_i ( req_i ), | ||
| .we_i ( we_i ), | ||
| .be_i ( be ), | ||
| .wdata_i ( wdata_user ), | ||
| .addr_i ( addr_i ), | ||
| .rdata_o ( rdata_user ) | ||
| ); | ||
| end else begin | ||
| logic [DATA_WIDTH-1:0] wdata_user; | ||
| logic [DATA_WIDTH-1:0] rdata_user; | ||
| logic [(DATA_WIDTH+7)/8-1:0] be; | ||
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| always_comb begin | ||
| wdata_user = wdata_i; | ||
| be = be_i; | ||
| rdata_o = rdata_user; | ||
| ruser_o = '0; | ||
| end | ||
| tc_sram_wrapper_cache_techno #( | ||
| .NumWords(NUM_WORDS), // Number of Words in data array | ||
| .DataWidth(DATA_AND_USER_WIDTH),// Data signal width | ||
| .ByteWidth(32'd8), // Width of a data byte | ||
| .NumPorts(32'd1), // Number of read and write ports | ||
| .Latency(32'd1), // Latency when the read data is available | ||
| .SimInit(SIM_INIT), // Simulation initialization | ||
| .BYTE_ACCESS(BYTE_ACCESS), // ACCESS byte or full word | ||
| .PrintSimCfg(1'b0) // Print configuration | ||
| ) i_tc_sram_wrapper ( | ||
| .clk_i ( clk_i ), | ||
| .rst_ni ( rst_ni ), | ||
| .req_i ( req_i ), | ||
| .we_i ( we_i ), | ||
| .be_i ( be ), | ||
| .wdata_i ( wdata_user ), | ||
| .addr_i ( addr_i ), | ||
| .rdata_o ( rdata_user ) | ||
| ); | ||
| end | ||
| end else begin | ||
| sram #( | ||
| .USER_WIDTH (USER_WIDTH), | ||
| .DATA_WIDTH (DATA_WIDTH), | ||
| .USER_EN (USER_EN), | ||
| .NUM_WORDS (NUM_WORDS) | ||
| ) data_sram ( | ||
| .clk_i (clk_i), | ||
| .rst_ni (rst_ni), | ||
| .req_i (req_i), | ||
| .we_i (we_i), | ||
| .addr_i (addr_i), | ||
| .wuser_i(wuser_i), | ||
| .wdata_i(wdata_i), | ||
| .be_i (be_i), | ||
| .ruser_o(ruser_o), | ||
| .rdata_o(rdata_o) | ||
| ); | ||
| end | ||
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| endmodule : sram_cache |
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| // Copyright 2022 Thales DIS design services SAS | ||
| // | ||
| // Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); | ||
| // you may not use this file except in compliance with the License. | ||
| // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 | ||
| // You may obtain a copy of the License at https://solderpad.org/licenses/ | ||
| // | ||
| // Original Author: Jean-Roch COULON - Thales | ||
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| // Copy of tc_sram_wrapper_cache | ||
| // To be replaced by the wrapper of the technology used to avoid having black box at synthesis | ||
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| module tc_sram_wrapper_cache_techno #( | ||
| parameter int unsigned NumWords = 32'd1024, // Number of Words in data array | ||
| parameter int unsigned DataWidth = 32'd128, // Data signal width | ||
| parameter int unsigned ByteWidth = 32'd8, // Width of a data byte | ||
| parameter int unsigned NumPorts = 32'd2, // Number of read and write ports | ||
| parameter int unsigned Latency = 32'd1, // Latency when the read data is available | ||
| parameter SimInit = "none", // Simulation initialization | ||
| parameter BYTE_ACCESS = 1, | ||
| parameter bit PrintSimCfg = 1'b0, // Print configuration | ||
| // DEPENDENT PARAMETERS, DO NOT OVERWRITE! | ||
| parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1, | ||
| parameter int unsigned BeWidth = (DataWidth + ByteWidth - 32'd1) / ByteWidth, // ceil_div | ||
| parameter type addr_t = logic [AddrWidth-1:0], | ||
| parameter type data_t = logic [DataWidth-1:0], | ||
| parameter type be_t = logic [BeWidth-1:0] | ||
| ) ( | ||
| input logic clk_i, // Clock | ||
| input logic rst_ni, // Asynchronous reset active low | ||
| // input ports | ||
| input logic [NumPorts-1:0] req_i, // request | ||
| input logic [NumPorts-1:0] we_i, // write enable | ||
| input addr_t [NumPorts-1:0] addr_i, // request address | ||
| input data_t [NumPorts-1:0] wdata_i, // write data | ||
| input be_t [NumPorts-1:0] be_i, // write byte enable | ||
| // output ports | ||
| output data_t [NumPorts-1:0] rdata_o // read data | ||
| ); | ||
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| // synthesis translate_off | ||
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| tc_sram #( | ||
| .NumWords(NumWords), | ||
| .DataWidth(DataWidth), | ||
| .ByteWidth(ByteWidth), | ||
| .NumPorts(NumPorts), | ||
| .Latency(Latency), | ||
| .SimInit(SimInit), | ||
| .PrintSimCfg(PrintSimCfg) | ||
| ) i_tc_sram ( | ||
| .clk_i ( clk_i ), | ||
| .rst_ni ( rst_ni ), | ||
| .req_i ( req_i ), | ||
| .we_i ( we_i ), | ||
| .be_i ( be_i ), | ||
| .wdata_i ( wdata_i ), | ||
| .addr_i ( addr_i ), | ||
| .rdata_o ( rdata_o ) | ||
| ); | ||
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| // synthesis translate_on | ||
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| endmodule |
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